سلام دوستان
من از کد زیر استفاده کردم تا ورودی 8 بیتی سریال بگیرم و بعد خروجی128بیتی موازی بگیرم و به ورودی برنامه رمزنگارم بفرستم.اینجا فقط بخش خروجی موازی گرفتن رو گذاشتم....آیا روشم اشتباهه؟
چون توی active hdl کامپایل نمیشه و ارور میده
این که توی component خودش یه component دیگه داره مشکل ایجاد نمیکنه؟
مرسی
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.aes_128.all;
---------------------------
------------------------------------------------ser to par
ENTITY DFF_1 IS
PORT(D,CLOCK2:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK2)
BEGIN
IF RISING_EDGE(CLOCK2) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;
--SUCCESS GETTING OUTPUT
--NOW DESIGN SHIFT REGISTER
--SERIAL TO PARALLEL CONVERTER AND SERIAL IN PARALLEL OUT SHIFT REGISTER ARE --BASICALLY SAME
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SERTOPAR IS
PORT(SERIN,CLOCK2:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SERTOPAR;
ARCHITECTURE BE1 OF SERTOPAR IS
SIGNAL S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;
BEGIN
D1:ENTITY WORK.DFF_1 PORT MAP(SERIN,CLOCK2,S1,OPEN);
Q(0)<=S1;
D2:ENTITY WORK.DFF_1 PORT MAP(S1,CLOCK2,S2,OPEN);
Q(1)<=S2;
D33:ENTITY WORK.DFF_1 PORT MAP (S2,CLOCK2,S3,OPEN);
Q(2)<=S3;
D4:ENTITY WORK.DFF_1 PORT MAP (S3,CLOCK2,S4,OPEN);
Q(3)<=S4;
D5:ENTITY WORK.DFF_1 PORT MAP (S4,CLOCK2,S5,OPEN);
Q(4)<=S5;
D6:ENTITY WORK.DFF_1 PORT MAP (S5,CLOCK2,S6,OPEN);
Q(5)<=S6;
D7:ENTITY WORK.DFF_1 PORT MAP (S6,CLOCK2,S7,OPEN);
Q(6)<=S7;
D8:ENTITY WORK.DFF_1 PORT MAP (S7,CLOCK2,Q(7),OPEN);
END BE1;
----------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity ENCRYPT is
port ( serial_in : in STD_LOGIC ;
clk: in std_logic;
rst: in std_logic;
D_EN:IN STD_LOGIC;
k_EN:IN STD_LOGIC;
DATA_out: out STD_LOGIC_VECTOR(127 downto 0));
end entity ENCRYPT;
---------------------------
architecture top_aes_RTL of ENCRYPT is
-------------------------------------
component SERTOPAR
PORT(SERIN,CLOCK2:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
--------------------------------------
SIGNAL D1 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D2 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D3 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D4 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D5 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D6 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D7 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D8 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D9 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D10 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D11 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D12 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D13 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D14 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D15 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D16 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL DATA_IN:STD_LOGIC_VECTOR (127 DOWNTO 0);
BEGIN
1 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D1 );
data_in (7 downto 0) <= q
wait for 100ns;
2 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D2 );
data_in (15 downto 8) <= q
wait for 100ns;
3 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D3 );
data_in (23 downto 16) <= q
wait for 100ns;
4 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D4 );
data_in (31 downto 24) <= q
wait for 100ns;
5 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D5 );
data_in (39 downto 32) <= q
wait for 100ns;
6 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D6 );
data_in (47 downto 40) <= q
wait for 100ns;
7 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D7 );
data_in (55 downto 48) <= q
wait for 100ns;
8 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D8 );
data_in (63 downto 56) <= q
wait for 100ns;
9 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D9 );
data_in (71 downto 64) <= q
wait for 100ns;
10 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D10 );
data_in (79 downto 72) <= q
wait for 100ns;
11 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D11 );
data_in (87 downto 80) <= q
wait for 100ns;
12 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D12 );
data_in (95 downto 88) <= q
wait for 100ns;
13 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D13 );
data_in (103 downto 96) <= q
wait for 100ns;
14 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D14 );
data_in (111 downto 104) <= q
wait for 100ns;
15 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D15 );
data_in (119 downto 112) <= q
wait for 100ns;
16 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D16 );
data_in (127 downto 120) <= q
END architecture top_aes_RTL of ENCRYPT ;
من از کد زیر استفاده کردم تا ورودی 8 بیتی سریال بگیرم و بعد خروجی128بیتی موازی بگیرم و به ورودی برنامه رمزنگارم بفرستم.اینجا فقط بخش خروجی موازی گرفتن رو گذاشتم....آیا روشم اشتباهه؟
چون توی active hdl کامپایل نمیشه و ارور میده
این که توی component خودش یه component دیگه داره مشکل ایجاد نمیکنه؟
مرسی
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.aes_128.all;
---------------------------
------------------------------------------------ser to par
ENTITY DFF_1 IS
PORT(D,CLOCK2:IN STD_LOGIC;Q,QBAR:OUT STD_LOGIC);
END DFF_1;
ARCHITECTURE FF OF DFF_1 IS
BEGIN
PROCESS(D,CLOCK2)
BEGIN
IF RISING_EDGE(CLOCK2) THEN
Q<=D;
QBAR<=NOT D;
END IF;
END PROCESS;
END FF;
--SUCCESS GETTING OUTPUT
--NOW DESIGN SHIFT REGISTER
--SERIAL TO PARALLEL CONVERTER AND SERIAL IN PARALLEL OUT SHIFT REGISTER ARE --BASICALLY SAME
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SERTOPAR IS
PORT(SERIN,CLOCK2:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SERTOPAR;
ARCHITECTURE BE1 OF SERTOPAR IS
SIGNAL S1,S2,S3,S4,S5,S6,S7,S8:STD_LOGIC;
BEGIN
D1:ENTITY WORK.DFF_1 PORT MAP(SERIN,CLOCK2,S1,OPEN);
Q(0)<=S1;
D2:ENTITY WORK.DFF_1 PORT MAP(S1,CLOCK2,S2,OPEN);
Q(1)<=S2;
D33:ENTITY WORK.DFF_1 PORT MAP (S2,CLOCK2,S3,OPEN);
Q(2)<=S3;
D4:ENTITY WORK.DFF_1 PORT MAP (S3,CLOCK2,S4,OPEN);
Q(3)<=S4;
D5:ENTITY WORK.DFF_1 PORT MAP (S4,CLOCK2,S5,OPEN);
Q(4)<=S5;
D6:ENTITY WORK.DFF_1 PORT MAP (S5,CLOCK2,S6,OPEN);
Q(5)<=S6;
D7:ENTITY WORK.DFF_1 PORT MAP (S6,CLOCK2,S7,OPEN);
Q(6)<=S7;
D8:ENTITY WORK.DFF_1 PORT MAP (S7,CLOCK2,Q(7),OPEN);
END BE1;
----------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity ENCRYPT is
port ( serial_in : in STD_LOGIC ;
clk: in std_logic;
rst: in std_logic;
D_EN:IN STD_LOGIC;
k_EN:IN STD_LOGIC;
DATA_out: out STD_LOGIC_VECTOR(127 downto 0));
end entity ENCRYPT;
---------------------------
architecture top_aes_RTL of ENCRYPT is
-------------------------------------
component SERTOPAR
PORT(SERIN,CLOCK2:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;
--------------------------------------
SIGNAL D1 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D2 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D3 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D4 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D5 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D6 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D7 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D8 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D9 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D10 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D11 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D12 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D13 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D14 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D15 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL D16 :STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL DATA_IN:STD_LOGIC_VECTOR (127 DOWNTO 0);
BEGIN
1 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D1 );
data_in (7 downto 0) <= q
wait for 100ns;
2 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D2 );
data_in (15 downto 8) <= q
wait for 100ns;
3 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D3 );
data_in (23 downto 16) <= q
wait for 100ns;
4 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D4 );
data_in (31 downto 24) <= q
wait for 100ns;
5 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D5 );
data_in (39 downto 32) <= q
wait for 100ns;
6 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D6 );
data_in (47 downto 40) <= q
wait for 100ns;
7 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D7 );
data_in (55 downto 48) <= q
wait for 100ns;
8 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D8 );
data_in (63 downto 56) <= q
wait for 100ns;
9 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D9 );
data_in (71 downto 64) <= q
wait for 100ns;
10 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D10 );
data_in (79 downto 72) <= q
wait for 100ns;
11 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D11 );
data_in (87 downto 80) <= q
wait for 100ns;
12 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D12 );
data_in (95 downto 88) <= q
wait for 100ns;
13 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D13 );
data_in (103 downto 96) <= q
wait for 100ns;
14 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D14 );
data_in (111 downto 104) <= q
wait for 100ns;
15 : SERTOPAR port map (SERIN => serial_in, Clock2 =>clk , q =>D15 );
data_in (119 downto 112) <= q
wait for 100ns;
16 : SERTOPAR port map (SERIN => serial_in , Clock2 =>clk , q =>D16 );
data_in (127 downto 120) <= q
END architecture top_aes_RTL of ENCRYPT ;
دیدگاه