assign out = start ? (in1 ^~ in2 ^~in3 ^~in4) : 1b'0;
entity shomaresh is
port (
output : out std_logic;
start: in std_logic ;
clk: in std_logic ;
input: in bit_vector (3 downto 0));
end entity;
architecture pr_arch of shomaresh is
begin
process (clk)
variable temp : integer range 0 to 3 :=0;
variable temp2 : integer range 0 to 3 :=0;
begin
if(clk'event and clk='1') then
if (start='1') then
if (input(0)='1') then
temp:=temp+1;
elsif (input(1)='1') then
temp:=temp+1;
elsif (input(2)='1') then
temp:=temp+1;
elsif (input(3)='1') then
temp:=temp+1;
end if;
temp2 := temp mod 2;
output <= '1' when temp2="xxxx" else
'0';
end if;
end if;
end process;
end pr_arch;
entity shomaresh is port ( output : out std_logic; start: in std_logic ; clk: in std_logic ; input: in std_logic_vector (3 downto 0)); end entity; architecture pr_arch of shomaresh is begin output <= (input(0) xnor input(1) xnor input(2) xnor input(3)) when start = '1' else 'Z'; end pr_arch;
entity shomaresh is port ( output : out std_logic; start: in std_logic ; clk: in std_logic ; input: in std_logic_vector (3 downto 0)); end entity; architecture pr_arch of shomaresh is begin process(clk) begin if rising_edge(clk) then if start = '1' then output <= input(0) xnor input(1) xnor input(2) xnor input(3); else output <= 'Z'; end if; end if; end process; end pr_arch;
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