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برنامه زیر رو خط :
TCCR2B | = (1<<CS21); // Prescaler at 8.
error می ده دلیلش چی می تونه باشه؟ سپاس از پاسخ شما
برنامه زیر رو خط :
TCCR2B | = (1<<CS21); // Prescaler at 8.
error می ده دلیلش چی می تونه باشه؟ سپاس از پاسخ شما
int f_signal=50; // Hz. Frequency desired for the output sine.
int f_pwm=62500; // Hz. PWM frequency.
// int TOP (int) (16000000/f_pwm)-1; // Top value for the resolution selected.
int TOP= 255;
//int n= (TOP * 2); // Length of the array.
int n= 510;
//int fs = n / 0.02; // Hz. Sampling frequency.
int i=0; // Cursor 1
int j= n/2. +1; // Cursor 2. The voltages must be 180 degrees shifted.
int dutycycle [510]; // Array that contains the values for the dutycycle.
// int dutycycle [n]; // It only works if the value is defined manually.
void setup () {
// PIN DEFINITION.
pinMode (9, OUTPUT);
pinMode (10, OUTPUT);
for (i=0; i<=n; i++)
{
dutycycle[i] = (int) ( (1 + sin (2.* PI *i/n ))* (TOP/2) + 0.5);
}
cli ( ); // Deactivating global interruptions
TCNT1= 0; // Initialize counter value to zero.
TCCR1A = (1<<COM1A1) | (1<<COM1B1) | (1<<WGM11);
// Non-inverting, fast PWM MODE. Clear OC1A/OC1B on Compare match. Mode 14.
TCCR1B= (1<<WGM13) | (1<<WGM12) | (1<<CS10);
// Counts from the bottom to the top and then decreases. No prescaling.
// ICR1= (int) (16000000 / f_pwm)-1;
// Overflow value. It sets the resolution of the PWM.
ICR1=TOP;
// In case another PWM frequency is desired, this value must be changed.
OCR1A= dutycycle[i]; // Dutycycle for pin 9
OCR1B= dutycycle[j]; // Dutycycle for pin 10
TCCR2A=0; // Setting the entire registers to zero.
TCCR2B=0;
TCCR2A | = (1<<WGM21); // Turn on Comparing Output Mode, non PWM.
TCCR2B | = (1<<CS21); // Prescaler at 8.
// In case it is changed, the formula below must be changed to the new prescaler.
//OCR2A = (byte) ((16000000 / (fs * 8) ) - 1);
// Number of pulses it counts until the interruption is activated.
OCR2A= 78;
TIMSK2 |= (1 << OCIE2A); // Timer 2 Output Compare Match A Interrupt Enable
sei ( ); // Global interruption activation
} //setup
void loop ( ) {
}
ISR (TIMER2_COMPA_vect) {
if (i<= n-1)
{
OCR1A= dutycycle [i];
i++;
}
else { i=0; } ;
if ( j<= n-1)
{
OCR1B= dutycycle[j];
j++;
}
else { j=0;}
}
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