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نمایش نتایج: از 1 به 4 از 4
  1. #1
    2006/10/29
    M.I.S
    631
    2

    آشنایی با چند اصطلاح

    CAD: Computer Aided Design
    HDL: Hardware Description Language
    DA: Design Automation
    VHSIC: Very High Speed Integrated Circuit
    VHDL: VHSIC Hardware Description Language
  2. #2
    2009/08/26
    68
    1
    EMP

    اصطلاحاتي كه در كاركردن با fpga با آن مواجه مي شويد

    ABEL – Advanced Boolean Expression Language, low-level language for design entry,
    from Data I/O.

    AIM – Advanced Interconnect Matrix in the CoolRunner-II CPLD that provides the flexible
    interconnection between the PLA function blocks.

    Antifuse – A small circuit element that can be irreversibly changed from being nonconducting
    to being conducting with ~100 Ohm. Anti-fuse-based FPGAs are thus nonvolatile
    and can be programmed only once (see OTP).

    AQL – Acceptable Quality Level. The relative number of devices, expressed in parts-permillion
    (ppm), that might not meet specification or be defective. Typical values are around
    10 ppm.

    ASIC – Application Specific Integrated Circuit, also called a gate array. Asynchronous logic
    that is not synchronized by a clock. Asynchronous designs can be faster than synchronous
    ones, but are more sensitive to parametric changes and are thus less robust.

    ASSP – Application-Specific Standard Product. Type of high-integration chip or chipset
    ASIC that is designed for a common yet specific application.

    ATM – Asynchronous Transfer Mode. A very high-speed (megahertz to gigahertz)
    connection-oriented bit-serial protocol for transmitting data and real-time voice and video in
    fixed-length packets (48-byte payload, 5-byte header).

    Back Annotation – Automatically attaching timing values to the entered design format
    after the design has been placed and routed in an FPGA.

    Behavioral Language – Top-down description from an even higher level than VHDL.

    Block RAM – A block of 2k to 4k bits of RAM inside an FPGA. Dual-port and synchronous
    operation are desirable.

    CAD – Computer Aided Design, using computers to design products.

    CAE – Computer Aided Engineering, analyses designs created on a computer.

    CLB – Configurable Logic Block. Xilinx-specific name for a block of logic surrounded by
    routing resources. A CLB contains two or four LUTs (function generators) plus two or four
    flip-flops.

    CMOS – Complementary Metal-Oxide-Silicon. Dominant technology for logic and memory.
    Has replaced the older bipolar TTL technology in most applications (except very fast ones).
    CMOS offers lower power consumption and smaller chip sizes compared to bipolar and
    now meets or even beats TTL speed


    Compiler – software that converts a higher language description into a lower-level
    representation. For FPGAs: the complete partition, place and route process.

    Configuration – The internally stored file that controls the FPGA so that it performs the
    desired logic function. Also, the act of loading an FPGA with that file.

    Constraints – Performance requirements imposed on the design, usually in the form of
    max allowable delay, or required operating frequency.

    CoolCLOCK – Combination of the clock divider and clock doubler functions in
    CoolRunner-II CPLDs to further reduce power consumption associated with high-speed
    clocked-in internal device networks.

    CPLD – Complex Programmable Logic Device, synonymous with EPLD. PAL-derived
    programmable logic devices that implement logic as sum-of- products driving macrocells.
    CPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have
    relatively high power consumption and fewer flip-flops compared to FPGAs.

    CUPL – Compiler Universal for Programmable Logic, CPLD development tool available
    from Logical Devices.

    DataGATE – A function within CoolRunner-II devices to block free-running input signals,
    effectively blocking controlled switching signals so they do not drive internal chip
    capacitances to further reduce power consumption. Can be selected on all inputs.

    Input Hysteresis – Input hysteresis provides designers with a tool to minimize external
    components, whether using the inputs to create a simple clock source or reducing the need
    for external buffers to sharpen a slow or noisy input signal. Function found in CoolRunner-
    II CPLDs (may also be referred to as Schmitt Trigger inputs in the text).

    DCM – Digital Clock Manager. Provides zero-delay clock buffering, precise phase control,
    and precise frequency generation on Xilinx Virtex-II FPGAs.

    DCI – Digitally Controlled Impedance in the Virtex-II solution dynamically eliminates drive
    strength variation due to process, temperature, and voltage fluctuation. DCI uses two
    external high-precision resistors to incorporate equivalent input and output impedance
    internally for hundreds of I/O pins.

    Debugging – The process of finding and eliminating functional errors in software and
    hardware.

    Density – Amount of logic in a device, often used to mean capacity. Usually measured in
    gates, but for FPGAs, better expressed in logic cells, each consisting of a 4-input LUT and
    a flip-flop.

    DLL – Delay Locked Loop, A digital circuit used to perform clock management functions
    on- and off-chip.

    DRAM – Dynamic Random Access Memory. A low-cost/read-write memory where data is
    stored on capacitors and must be refreshed periodically. DRAMs are usually addressed by
    a sequence of two addresses – row address and column address – which makes them
    slower and more difficult to use than SRAMs.

    DSP – Digital Signal Processing. The manipulation of analog data that has been sampled
    and converted into a digital representation. Examples are filtering, convolution, and Fast
    Fourier Transform
    EAB – Embedded Array Block. Altera™ name for block RAM in FLEX10K.

    EDIF – Electronic Data Interchange Format. Industry-standard for specifying a logic design
    in text (ASCII) form
    EPLD – Erasable Programmable Logic Devices, synonymous with CPLDs. PAL-derived
    programmable logic devices that implement logic as sum-of- products driving macrocells.
    EPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have
    relatively high power consumption and fewer flip-flops than FPGAs.

    Embedded RAM – Read-write memory stored inside a logic device. Avoids the delay and
    additional connections of an external RAM.

    ESD – Electro-Static Discharge. High-voltage discharge can rupture the input transistor
    gate oxide. ESD-protection diodes divert the current to the supply leads.

    5-Volt Tolerant – Characteristic of the input or I/O pin of a 3.3V device that allows this pin
    to be driven to 5V without any excessive input current or device breakdown. Very desirable
    feature.

    FIFO – First-In-First-Out memory, where data is stored in the incoming sequence and is
    read out in the same sequence. Input and output can be asynchronous to each other. A
    FIFO needs no external addresses, although all modern FIFOs are implemented internally
    with RAMs driven by circular read and write counters.

    FIT – Failure In Time. Describes the number of device failures statistically expected for a
    certain number of device-hours. Expressed as failures per one billion device hours. Device
    temperature must be specified. MTBF can be calculated from FIT.

    Flash – Non-volatile programmable technology, an alternative to Electrically-Erasable
    Programmable Read-Only Memory (EEPROM) technology. The memory content can be
    erased by an electrical signal. This allows in-system programmability and eliminates the
    need for ultraviolet light and quartz windows in the package.

    Flip-Flop – Single-bit storage cell that samples its Data input at the active (rising or falling)
    clock edge, and then presents the new state on its Q output after that clock edge, holding
    it there until after the next active clock edge.

    Floorplanning – Method of manually assigning specific parts of the design to specific chip
    locations. Can achieve faster compilation, better utilization, and higher performance.

    Footprint – The printed circuit pattern that accepts a device and connects its pins
    appropriately. Footprint-compatible devices can be interchanged without modifying the PC
    board.

    FPGA – Field Programmable Gate Array. An integrated circuit that contains configurable
    (programmable) logic blocks and configurable (programmable) interconnect between
    those blocks.

    Function Generator – Also called look-up-table, with N-inputs and one output. Can
    implement any logic function of its N-inputs. N is between 2 and 6; 4-input function
    generators are most popular.

    GAL – Generic Array Logic. Lattice name for a variation on PALs Gate. Smallest logic
    element with several inputs and one output. AND gate output is high when all inputs are
    high. OR gate output is high when at least one input is high. A 2-input NAND gate is used
    as the measurement unit for gate array complexity.

    Gate Array – ASIC where transistors are pre-defined, and only the interconnect pattern is
    customized for the individual application.

    GTL – Gunning Transceiver Logic. A high-speed, low-power back-plane standard.

    GUI – Graphic User Interface. A way of representing the computer output on the screen as
    graphics, pictures, icons, and windows. Pioneered by Xerox and the Macintosh, now
    universally adopted (e.g., by Windows 95).
    HDL – Hardware Description Language.

    Hierarchical Design – Design description in multiple layers, from the highest (overview) to
    the lowest (circuit details). Alternative: flat design, where everything is described at the
    same level of detail. Incremental design making small design changes while maintaining
    most of the layout and routing.

    Interconnect – Metal lines and programmable switches that connect signals between logic
    blocks and between logic blocks and the I/O.

    IOB or I/O – Input/Output block. Logic block with features specialized for interfacing with
    the PC board.

    ISO9000 – An internationally recognized quality standard. Xilinx is certified to ISO9001 and
    ISO9002.

    IP – Intellectual Property. In the legal sense: patents, copyrights, and trade secrets. In
    integrated circuits: pre-defined large functions, called cores, that help you complete large
    designs faster.

    ISP – In-System Programmable device. A programmable logic device that can be
    programmed after it has been connected to (soldered into) the system PC board. Although
    all SRAM-based FPGAs are naturally ISP, this term is only used with certain CPLDs, to
    distinguish them from the older CPLDs that must be programmed in programming
    equipment.

    JTAG – Joint Test Action Group. Older name for IEEE 1149.1 Boundary Scan, a method to
    test PC boards and ICs.

    LogiBLOX – Formerly called X-Blox. Library of logic modules, often with user-definable
    parameters, like data width. Very similar to LPM.

    Logic Cell – Metric for FPGA density. One logic cell is one 4-input look-up table plus one
    flip-flop.

    LPM – Library of Parameterized Modules. Library of logic modules, often with userdefinable
    parameters, like data width. Very similar to LogiBlox.

    LUT – Look-Up Table. Also called function generator with N inputs and one output. Can
    implement any logic function of its N inputs. N is between 2 and 6; 4-input LUTs are most
    popular.

    Macrocell – The logic cell in a sum-of-products CPLD or PAL/GAL.

    Mapping – Process of assigning portions of the logic design to the physical chip resources
    (CLBs). With FPGAs, mapping is a more demanding and more important process than with
    gate arrays.

    MTBF – Mean Time Between Failure. The statistically relevant up-time between equipment
    failure. See also FIT.

    Netlist – Textual description of logic and interconnects. See also XNF and EDIF.

    NRE – Non-Recurring Engineering charges. Startup cost for the creation of an ASIC, gate
    array, or HardWire. Pays for layout, masks, and test development. FPGAs and CPLDs do
    not require NRE.

    Optimization – Design change to improve performance. See also Synthesis.

    OTP – One-Time Programmable. Irreversible method of programming logic or memory.
    Fuses and anti-fuses are inherently OTP. EPROMs and EPROM-based CPLDs are OTP if
    their plastic package blocks the ultraviolet light needed to erase the stored data or
    configuration
    PAL – Programmable Array Logic. Oldest practical form of programmable logic,
    implemented a sum-of-products plus optional output flip-flops.

    Partitioning – In FPGAs, the process of dividing the logic into sub-functions that can later
    be placed into individual CLBs. Partitioning precedes placement.

    PCI – Peripheral Component Interface. Synchronous bus standard characterized by short
    range, light loading, low cost, and high performance. A 33 MHz PCI can support data byte
    transfers of up to 132 megabytes per second on 36 parallel data lines (including parity) and
    a common clock. There is also a new 66 MHz standard.

    PCMCIA – Personal Computer Memory Card Interface Association. (Also: People Can’t
    Memorize Computer Industry Acronyms). Physical and electrical standard for small plug-in
    boards for portable computers.

    Pin-Locking – Rigidly defining and maintaining the functionality and timing requirements
    of device pins while the internal logic is still being designed or modified. Pin-locking has
    become important, since circuit-board fabrication times are longer than PLD design
    implementation times.

    PIP – Programmable Interconnect Point. In Xilinx FPGAs, a point where two signal lines
    can be connected, as determined by the device configuration.

    Placement – In FPGAs, the process of assigning specific parts of the design to specific
    locations (CLBs) on the chip. Usually done automatically.

    PLA – Programmable Logic Array. The first and most flexible programmable logic
    configuration with two programmable planes providing any combination of “AND” and “OR”
    gates and sharing of AND terms across multiple ORs. This architecture is implemented in
    CoolRunner and CoolRunner-II devices.

    PLD – Programmable Logic Device. Most generic name for all programmable logic: PALs,
    CPLDs, and FPGAs.

    QML – Qualified Manufacturing Line. For example, ISO9000.

    Routing – The interconnection, or the process of creating the desired interconnection, of
    logic cells to make them perform the desired function. Routing follows partitioning and
    placement.

    Schematic – Graphic representation of a logic design in the form of interconnected gates,
    flip-flops, and larger blocks. Older and more visually intuitive alternative to the increasingly
    more popular equation-based or high-level language text description of a logic design.

    SelectRAM – Xilinx-specific name for a small RAM (usually 16 bits), implemented in a LUT.

    Simulation – Computer modeling of logic and (sometimes) timing behavior of logic driven
    by simulation inputs (stimuli or vectors).

    SPROM – Serial Programmable Read-Only Memory. Non-volatile memory device that can
    store the FPGA configuration bitstream. The SPROM has a built-in address counter,
    receives a clock, and outputs a serial bitstream.

    SRAM – Static Random Access Memory. Read-write memory with data stored in latches.
    Faster than DRAM and with simpler timing requirements, but smaller in size and about four
    times as expensive than DRAM of the same capacity.

    SRL16 – Shift Register LUT, an alternative mode of operation for every function generator
    (LUT) that are part of every CLB in Virtex and Spartan FPGAs. This mode increases the
    number of flip-flops by 16. Adding flip-flops enables fast pipelining – ideal in DSP
    applications.
    Static Timing – Detailed description of on-chip logic and interconnect delays.

    Sub-Micron – The smallest feature size is usually expressed in micron (μ = millionth of a
    meter, or thousandth of a millimeter) The state of the art is moving from 0.35μ to 0.25μ, and
    may soon reach 0.18μ. The wavelength of visible light is 0.4 to 0.8μ. 1 mil = 25.4μ.

    Synchronous – Circuitry that changes state only in response to a common clock, as
    opposed to asynchronous circuitry that responds to a multitude of derived signals.
    Synchronous circuits are easier to design, debug, and modify, and tolerate parameter
    changes and speed upgrades better than asynchronous circuits.

    Synthesis – Optimization process of adapting a logic design to the logic resources
    available on the chip, like LUTs, longline, and dedicated carry. Synthesis precedes
    mapping.

    SystemI/O – Technology incorporated in Virtex-II FPGAs that uses the SelectIO-Ultra
    blocks to provide the fastest and most flexible electrical interfaces available. Each I/O pin
    is individually programmable for any of the 19 single-ended I/O standards or six differential
    I/O standards, including LVDS, SSTL, HSTL II, and GTL+. SelectIO-Ultra technology
    delivers 840 Mbps LVDS performance using dedicated DDR registers.

    TBUFs – Buffers with a tri-state option, where the output can be made inactive. Used for
    multiplexing different data sources onto a common bus. The pull- down-only option can use
    the bus as a wired AND function.

    Timing – Relating to delays, performance, or speed.

    Timing Driven – A design or layout method that takes performance requirements into
    consideration.

    UART – Universal Asynchronous Receiver/Transmitter. An 8-bit-parallel- to-serial and
    serial-to-8-bit-parallel converter, combined with parity and start- detect circuitry and
    sometimes even FIFO buffers. Used widely in asynchronous serial communications
    interfaces such as modems.

    USB – Universal Serial Bus. A new, low-cost, low-speed, self-clocking bit- serial bus (1.5
    MHz and 12 MHz) using four wires (Vcc, ground, differential data) to daisy-chain as many
    as 128 devices.

    VME – Older bus standard, popular with MC68000-based industrial computers.

    XA – Device suffix for automotive parts.

    XNF File – Xilinx proprietary description format for a logic design Alternative: EDIF.
  3. #3
    2009/08/26
    68
    1
    EMP

    پاسخ : آشنایی با چند اصطلاح

    ABEL Advanced Boolean Expression Language
    ADC Analog-to-Digital Converter
    AIM Advanced Interconnect Matrix
    ANSI American National Standards Institute
    ASIC Application Specific Integrated Circuit
    ASSP Application Specific Standard Product
    ATE Automatic Test Equipment
    BGA Ball Grid Array
    BLVDS Backplane Low Voltage Differential Signaling
    BUFG Global Clock Buffer
    CAD Computer Aided Design
    CAN Controller Area Network
    CBT Computer Based Training
    CDMA Code Division Multiple Access
    CE Clock Enable
    CLB Configurable Logic Block
    CLK Clock Signal
    CMOS Complementary Metal Oxide Semiconductor
    CPLD Complex Programmable Logic Device
    CSP Chip Scale Packaging
    DCI Digitally Controlled Impedance
    DCM Digital Clock Manager
    DCM Digital Control Management
    DES Data Encryption Standard
    DRAM Dynamic Random Access Memory
    DRC Design Rule Checker
    DSL Digital Subscriber Line
    DSP Digital Signal Processor
    DTV Digital Television
    ECS Schematic Editor
    EDA Electronic Design Automation
    EDIF Electronic Digital Interchange Format
    EMI Electromagnetic Interference
    EPROM Erasable Programmable Read Only Memory
    eSP emerging Standards and Protocols
    FAT File Allocation Table
    FIFO First In First Out
    FIR Finite Impulse Response (Filter)
    FIT Failures in Time
    FLBGA Flip Chip Ball Grid Array
    fMax Frequency Maximum
    FPGA Field Programmable Gate Array
    FSM Finite State Machine
    GPS Global Positioning System
    GTL Gunning Transceiver Logic
    GTLP Gunning Transceiver Logic Plus
    GUI Graphical User Interface
    HDL Hardware Description Language
    HDTV High Definition Television
    HEX Hexadecimal
    HSTL High Speed Transceiver Logic
    I/O Inputs and Outputs
    IBIS I/O Buffer Information Specification
    IEEE Institute of Electrical and Electronics Engineers
    ILA Integrated Logic Analyzer
    IOB Input Output Block
    IP Intellectual Property
    IRL Internet Reconfigurable Logic
    ISE Integrated Software Environment
    ISP In System Programming
    JEDEC Joint Electron Device Engineering Council
    JTAG Joint Test Advisory Group
    LAN Local Area Network
    LEC Logic Equivalence Checker
    LMG Logic Modeling Group
    LSB Least Significant Bit
    LUT Look Up Table
    LVCMOS Low Voltage Complementary Metal Oxide Semiconductor
    LVDS Low Voltage Differential Signaling
    LVDSEXTLow Voltage Differential Signaling Extension
    LVPECL Low Voltage Positive Emitter Coupled Logic
    LVTTL Low Voltage Transistor to Transistor Logic
    MAC Multiply and Accumulate
    MAN Metropolitan Area Network
    MCS Manipulate Comment Section
    MIL Military
    MOSFET Metal Oxide Semiconductor Field Effect Transistors
    MP3 MPEG Layer III Audio Coding
    MPEG Motion Picture Experts Group
    MSB Most Significant Bit
    MUX Multiplexer
    NAND Not And
    NGC Native Generic Compiler
    NRE Non-Recurring Engineering (Cost)
    OE Output Enable
    OTP One Time Programmable
    PACE Pinout and Area Constraints Editor
    PAL Programmable Array Logic
    PCB Printed Circuit Board
    PCI Peripheral Component Interconnect
    PCMCIA Personal Computer Memory Card International Association
    PCS Personnel Communications System
    PLA Programmable Logic Array
    PLD Programmable Logic Device
    PROM Programmable Read Only Memory
    QFP Quad Flat Pack
    QML Qualified Manufacturers Listing
    QPRO QML Performance Reliability of Supply Off the Shelf ASIC
    RAM Random Access Memory
    RC Radio Controlled
    ROM Read Only Memory
    SOP Sum of Product
    SPLD Simple Programmable Logic Device
    SRAM Static Random Access Memory
    SRL16 Shift Register LUT
    SSTL Stub Series Terminated Transceiver Logic
    TIM Time in Market
    Tpd Time of Propagation Delay (through the device)
    TQFP Thin Quad Flat Pack
    TTM Time to Market
    UCF User Constraints File
    UMTS Universal Mobile Telecommunications System
    UV Ultraviolet
    VCCO Voltage Current Controlled Oscillator
    VFM Variable Function Multiplexer
    VHDL VHISC High Level Description Language
    VHSIC Very High Speed Integrated Circuit
    VREF Voltage Reference
    VSS Visual Software Solutions
    WAN Wireless Area Network
    WLAN Wireless Local Access Network
    WPU Weak Pull Up
    XCITE Xilinx Controlled Impedance Technology
    XOR Exclusive OR
    XST Xilinx Synthesis Technology
    ZIA Zero Power Interconnect Array

  4. #4
    2006/10/29
    M.I.S
    631
    2

    پاسخ : آشنایی با چند اصطلاح

    دوست عزیز ممنون بابت این اصطلاح ها میتونستی جای دیگه بذاریشون من میخواستم چندتا مطلب بذارم در مورد vhdl و fpga که اینها رو گفتم قبلش بذارم برای آشنایی شما اینجا رو حسابی شلوغ کردی :applause:
نمایش نتایج: از 1 به 4 از 4

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