اطلاعیه

Collapse
No announcement yet.

پروژه ماشین حساب fpga

Collapse
X
 
  • فیلتر
  • زمان
  • Show
Clear All
new posts

    پروژه ماشین حساب fpga

    من یه پروژه از اینترنت پیدا کردم در مورد ماشین حساب. کدهاشونو براتون می زارم. من نیاز دارم به یه پروژه ماشین حساب ک عملیات ساده رو انجام بده و همچنین عملیات logic & shift right , shift left که از keyboard اعداد وارد شه. با انجام چه تغییراتی رو این کدها می تونم به چیزی که می خوام برسم. ممنون می شم اگه کمکم کنید و وقت زیادیم ندارم. مرسی

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity calc1 is
    Port ( Clk : in std_logic;
    Switches : in std_logic_vector(7 downto 0);
    Buttons : in std_logic_vector(6 downto 0);
    Result : out std_logic_vector(7 downto 0));
    end calc1;

    architecture Behavioral of calc1 is
    Signal Q0,Q1,Q2,Q3: std_logic_vector(7 downto 0) := (others=>'0'
    Signal S: std_logic_vector(1 downto 0);
    Signal S3S2S1S0: std_logic_vector(3 downto 0);
    Signal D,B,T: std_logic_vector(7 downto 0);
    signal Old_buttons: std_logic_vector(6 downto 0);
    begin
    T <= Switches;
    B <= (others=>'0'
    Result <= Q0;

    One_puls_detector:
    process( clk)
    variable One_pulses: std_logic_vector(6 downto 0);
    begin
    if rising_edge( Clk) then
    Old_buttons <= Buttons;
    One_pulses := not Old_buttons and Buttons;
    case One_pulses is
    when "0000001" => S <= "01"; S3S2S1S0 <= "0000"; -- Enter
    when "0000010" => S <= "10"; S3S2S1S0 <= "0000"; -- Pop
    when "0000100" => S <= "11"; S3S2S1S0 <= "0001"; -- +
    when "0001000" => S <= "11"; S3S2S1S0 <= "0010"; -- -
    when "0010000" => S <= "11"; S3S2S1S0 <= "0100"; -- *
    when "0100000" => S <= "11"; S3S2S1S0 <= "1000"; -- /
    when "1000000" => S <= "11"; S3S2S1S0 <= "1111"; -- XOR
    when others => S <= "00"; S3S2S1S0 <= "0000"; -- nop
    end case;
    end if;
    end process;

    The_RPN_Stack:
    process( Clk)
    begin
    if rising_edge( Clk) then
    case S is
    When "00" => Null;
    When "01" => Q3<=Q2; Q2<=Q1; Q1<=Q0; Q0<=T;
    When "10" => Q0<=Q1; Q1<=Q2; Q2<=Q3; Q3<=B;
    When "11" => Q0<=D; Q1<=Q2; Q2<=Q3; Q3<=B;
    When others => Null;
    end case;
    end if;
    end process;

    ALU_process:
    process( S3S2S1S0, Q1, Q0)
    begin
    case S3S2S1S0 is
    when "0001" => D <= Q1+Q0;
    when "0010" => D <= Q1-Q0;
    when "0100" => D <= Q1(3 downto 0) * Q0(3 downto 0);
    -- When "1000" => D <= Q1/Q0; -- This one tricky - make a ROM
    when "1111" => D <= Q1 xor Q0;
    when others => D <= (others=>'0'
    end case;
    end process;
    end Behavioral;

    Added after 6 minutes:

    could anyone explain about this code since this program is about RPN calculator which i;m not familiar with

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity calc1 is
    Port ( Clk : in std_logic;
    Switches : in std_logic_vector(7 downto 0);
    Buttons : in std_logic_vector(6 downto 0);
    Result : out std_logic_vector(7 downto 0));
    end calc1;

    architecture Behavioral of calc1 is
    Signal Q0,Q1,Q2,Q3: std_logic_vector(7 downto 0) := (others=>'0'
    Signal S: std_logic_vector(1 downto 0);
    Signal S3S2S1S0: std_logic_vector(3 downto 0);
    Signal D,B,T: std_logic_vector(7 downto 0);
    signal Old_buttons: std_logic_vector(6 downto 0);
    begin
    T <= Switches;
    B <= (others=>'0'
    Result <= Q0;

    One_puls_detector:
    process( clk)
    variable One_pulses: std_logic_vector(6 downto 0);
    begin
    if rising_edge( Clk) then
    Old_buttons <= Buttons;
    One_pulses := not Old_buttons and Buttons;
    case One_pulses is
    when "0000001" => S <= "01"; S3S2S1S0 <= "0000"; -- Enter
    when "0000010" => S <= "10"; S3S2S1S0 <= "0000"; -- Pop
    when "0000100" => S <= "11"; S3S2S1S0 <= "0001"; -- +
    when "0001000" => S <= "11"; S3S2S1S0 <= "0010"; -- -
    when "0010000" => S <= "11"; S3S2S1S0 <= "0100"; -- *
    when "0100000" => S <= "11"; S3S2S1S0 <= "1000"; -- /
    when "1000000" => S <= "11"; S3S2S1S0 <= "1111"; -- XOR
    when others => S <= "00"; S3S2S1S0 <= "0000"; -- nop
    end case;
    end if;
    end process;

    The_RPN_Stack:
    process( Clk)
    begin
    if rising_edge( Clk) then
    case S is
    When "00" => Null;
    When "01" => Q3<=Q2; Q2<=Q1; Q1<=Q0; Q0<=T;
    When "10" => Q0<=Q1; Q1<=Q2; Q2<=Q3; Q3<=B;
    When "11" => Q0<=D; Q1<=Q2; Q2<=Q3; Q3<=B;
    When others => Null;
    end case;
    end if;
    end process;

    ALU_process:
    process( S3S2S1S0, Q1, Q0)
    begin
    case S3S2S1S0 is
    when "0001" => D <= Q1+Q0;
    when "0010" => D <= Q1-Q0;
    when "0100" => D <= Q1(3 downto 0) * Q0(3 downto 0);
    -- When "1000" => D <= Q1/Q0; -- This one tricky - make a ROM
    when "1111" => D <= Q1 xor Q0;
    when others => D <= (others=>'0'
    end case;
    end process;
    end Behavioral;
    [move][move][/move][/move]

    #2
    پاسخ : پروژه ماشین حساب fpga

    یه سری کد هم پیدا کردم که فکر کنم این بهتره ولی عملیات logic & shift رو نداره.می شه کمکم کنید که این عملیات رو هم توش جا بدم؟

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity calculator is
    port(A,B : in integer range 0 to 7;
    clk : in bit;
    sel : in std_logic_vector(1 downto 0);
    Q : out bit_vector(6 downto 0);
    An : out bit_vector(3 downto 0));

    end calculator;

    architecture Behavioral of calculator is
    signal sub : integer range 0 to 7;
    signal sum : integer range 0 to 14;
    signal div : integer range 0 to 7;
    signal Mul : integer range 0 to 49;

    signal Qsub,Qsum1,Qsum2,Qmul,Qmul2,Qdiv :bit_vector(6 downto 0);
    signal minus : bit_vector(6 downto 0);

    signal divRemainder:bit_vector(6 downto 0);
    signal B1:bit_vector(6 downto 0);

    signal clk1: bit;


    begin

    clkDiv : process
    variable count :integer range 0 to 50000000;
    begin
    wait until clk'event and clk='1';
    count := count + 1;
    if (count = 50000000) then
    count := 0;
    elsif (count < 25000000) then
    clk1 <= '0';
    elsif (count > 25000000) then
    clk1 <= '1';
    end if;
    end process clkDiv;


    sub_opration : process(A,B)
    begin


    if(A>B) then
    sub<=A-B;
    minus<="1111111";
    case sub is
    when 0 =>Qsub <="1000000";
    when 1 =>Qsub<="1111001";
    when 2 =>Qsub<="0100100";
    when 3 =>Qsub<="0110000";
    when 4 =>Qsub<="0011001";
    when 5 =>Qsub<="0010010";
    when 6 =>Qsub<="0000010";
    when 7 =>Qsub<="1011000";
    when others => null;
    end case;

    else
    sub<=B-A;
    minus<="0111111";
    case sub is
    when 0 =>Qsub<="1000000";
    when 1 =>Qsub<="1111001";
    when 2 =>Qsub<="0100100";
    when 3 =>Qsub<="0110000";
    when 4 =>Qsub<="0011001";
    when 5 =>Qsub<="0010010";
    when 6 =>Qsub<="0000010";
    when 7 =>Qsub<="1011000";
    when others => null;
    end case;
    end if;


    end process sub_opration;

    sum_opration : process(A,B)
    begin

    sum<=A+B;

    case sum is

    when 0 =>Qsum1<="1000000";
    Qsum2<="1111111";
    when 1 =>Qsum1<="1111001";
    Qsum2<="1111111";
    when 2 =>Qsum1<="0100100";
    Qsum2<="1111111";
    when 3 =>Qsum1<="0110000";
    Qsum2<="1111111";
    when 4 =>Qsum1<="0011001";
    Qsum2<="1111111";
    when 5 =>Qsum1<="0010010";
    Qsum2<="1111111";
    when 6 =>Qsum1<="0000010";
    Qsum2<="1111111";
    when 7 =>Qsum1<="1011000";
    Qsum2<="1111111";
    when 8 =>Qsum1<="0000000";
    Qsum2<="1111111";
    when 9 =>Qsum1<="0010000";
    Qsum2<="1111111";
    when 10=>Qsum1<="1000000";
    Qsum2<="1111001";
    when 11=>Qsum1<="1111001";
    Qsum2<="1111001";
    when 12=>Qsum1<="0100100";
    Qsum2<="1111001";
    when 13=>Qsum1<="0110000";
    Qsum2<="1111001";
    when 14=>Qsum1<="0011001";
    Qsum2<="1111001";
    when others => null;
    end case;


    end process sum_opration;

    Mul_operation : process(A,B)
    variable Remm10:integer range 0 to 9;
    variable C1: integer range 1 to 7 :=7;
    begin
    Mul<= A*B;

    if(Mul<10) then
    case Mul is
    when 0 =>Qmul<="1000000";
    Qmul2<="1111111";
    when 1 =>Qmul<="1111001";
    Qmul2<="1111111";
    when 2 =>Qmul<="0100100";
    Qmul2<="1111111";
    when 3 =>Qmul<="0110000";
    Qmul2<="1111111";
    when 4 =>Qmul<="0011001";
    Qmul2<="1111111";
    when 5 =>Qmul<="0010010";
    Qmul2<="1111111";
    when 6 =>Qmul<="0000010";
    Qmul2<="1111111";
    when 7 =>Qmul<="1011000";
    Qmul2<="1111111";
    when 8 =>Qmul<="0000000";
    Qmul2<="1111001";
    when 9 =>Qmul<="0010000";
    Qmul2<="1111111";
    when others => null;
    end case;

    else
    for j in 7 downto 1 loop

    if(10*C1<Mul or 10*C1= Mul)then
    Mul<=10*C1;
    Remm10:=10*C1-Mul;
    end if;
    C1:=C1-1;

    end loop;

    case Mul is
    when 0 =>Qmul2<="1000000";
    when 1 =>Qmul2<="1111001";
    when 2 =>Qmul2<="0100100";
    when 3 =>Qmul2<="0110000";
    when 4 =>Qmul2<="0011001";
    when 5 =>Qmul2<="0010010";
    when 6 =>Qmul2<="0000010";
    when 7 =>Qmul2<="1011000";
    when 8 =>Qmul2<="0000000";
    when 9 =>Qmul2<="0010000";
    when others => null;
    end case;

    case Remm10 is
    when 0 =>Qmul<="1000000";
    when 1 =>Qmul<="1111001";
    when 2 =>Qmul<="0100100";
    when 3 =>Qmul<="0110000";
    when 4 =>Qmul<="0011001";
    when 5 =>Qmul<="0010010";
    when 6 =>Qmul<="0000010";
    when 7 =>Qmul<="1011000";
    when 8 =>Qmul<="0000000";
    when 9 =>Qmul<="0010000";
    when others => null;
    end case;

    end if;

    end process Mul_operation;

    div_operation: process(A,B)
    variable C : integer range 1 to 7 :=7;
    variable Remm:integer range 0 to 9;
    begin

    for I in 7 downto 1 loop

    if(A=B)then
    div<=1;
    Remm:=0;

    elsif(B>A)then
    div<=0;

    elsif(A>B)then
    if(B*C<A)then
    div<=B*C;
    Remm:=B*C-A; --the result will display as: div _| Remainder _| B
    end if;
    C:=C-1;
    end if;

    end loop;

    case div is
    when 0 =>Qdiv<="1000000";
    when 1 =>Qdiv<="1111001";
    when 2 =>Qdiv<="0100100";
    when 3 =>Qdiv<="0110000";
    when 4 =>Qdiv<="0011001";
    when 5 =>Qdiv<="0010010";
    when 6 =>Qdiv<="0000010";
    when 7 =>Qdiv<="1011000";
    when others => null;
    end case;

    case Remm is
    when 0 =>divRemainder<="1000000";
    when 1 =>divRemainder<="1111001";
    when 2 =>divRemainder<="0100100";
    when 3 =>divRemainder<="0110000";
    when 4 =>divRemainder<="0011001";
    when 5 =>divRemainder<="0010010";
    when 6 =>divRemainder<="0000010";
    when 7 =>divRemainder<="1011000";
    when others => null;
    end case;

    case B is
    when 0 =>B1<="1000000";
    when 1 =>B1<="1111001";
    when 2 =>B1<="0100100";
    when 3 =>B1<="0110000";
    when 4 =>B1<="0011001";
    when 5 =>B1<="0010010";
    when 6 =>B1<="0000010";
    when 7 =>B1<="1011000";
    when others => null;
    end case;

    end process div_operation;


    choice : process(clk1,sel)
    variable m : integer range 0 to 3 := 0;
    begin
    if(clk1'event and clk1 = '1&#039 then

    case m is
    when 0 =>
    if(sel = "00&quot then
    Q <= Qsub;
    elsif(sel="01&quot then
    Q<=Qsum1;
    elsif(sel="10&quot then
    Q<=Qmul;
    elsif(sel="11&quot then
    Q<=B1;
    end if;
    An<="1110";

    when 1 =>
    if(sel = "00&quot then
    Q <= minus;
    elsif(sel="01&quot then
    Q<=Qsum2;
    elsif(sel="10&quot then
    Q<=Qmul2;
    elsif(sel="11&quot then
    Q<="1110011"; -- display _|
    end if;
    An<="1101";

    when 2 =>
    if(sel="11&quot then
    Q<= divRemainder;
    end if;
    An<="1011";

    when 3 =>
    if (sel="11&quot then
    Q<= Qdiv;
    end if;
    An<="0111";

    end case;
    m := m + 1;
    end if;
    end process choice;
    end Behavioral;

    دیدگاه


      #3
      پاسخ : پروژه ماشین حساب fpga

      باز یه سری کد جدید پیدا کردم می شه فرق این رو با قبلیه بگین؟

      --- Code for LSU EE 4702 Spring 2001

      --- Calculator Example


      library ieee;
      use ieee.std_logic_1164.all;
      library Std_DevelopersKit;
      use Std_DevelopersKit.Std_Regpak.all;

      --- Definitions used by calculator code and testbench.

      package calc_defs is
      type key_t is array ( 5 downto 0 ) of std_logic;

      -- These must be initialized by string literals to be used in a case stmt.
      constant key_none : key_t := o"00";
      constant key_never : key_t := o"01";

      constant key_plus : key_t := o"10";
      constant key_minus : key_t := o"11";
      constant key_times : key_t := o"12";
      constant key_divide : key_t := o"13";
      constant key_equal : key_t := o"14";
      constant key_clear : key_t := o"15";

      constant key_0 : key_t := o"20";
      constant key_1 : key_t := o"21";
      constant key_2 : key_t := o"22";
      constant key_3 : key_t := o"23";
      constant key_4 : key_t := o"24";
      constant key_5 : key_t := o"25";
      constant key_6 : key_t := o"26";
      constant key_7 : key_t := o"27";
      constant key_8 : key_t := o"30";
      constant key_9 : key_t := o"31";

      end calc_defs;

      --- Calculator

      library ieee;
      use ieee.std_logic_1164.all;
      library Std_DevelopersKit;
      use Std_DevelopersKit.Std_Regpak.all;
      use work.calc_defs.all;


      entity calc is
      generic( precision: integer := 32 );
      port( display_val : out std_logic_vector ( precision-1 downto 0 );
      beep : out std_logic;
      key_code : in key_t;
      reset : in std_logic;
      clk : in std_logic);
      end calc;

      architecture a1 of calc is

      -- Internally used constants for categorizing keys.
      constant kty_digit: key_t := o"40";
      constant kty_arith: key_t := o"41";

      -- Other constants.
      constant buffer_max:integer := ( 2 ** precision ) - 1;
      constant zero: std_logic_vector ( precision-1 downto 0 ) := ( others => '0' );

      type state_t is (st_0N, st_0P, st_0C, st_1N, st_1P);

      signal beep_time : std_logic_vector ( 5 downto 0 );
      signal beep_ack, beep_req : std_logic;
      signal pending_op : key_t;
      signal state : state_t;
      signal cbuffer, acc : std_logic_vector ( precision-1 downto 0 );

      impure function do_op return std_logic_vector is
      begin
      case pending_op is
      when key_plus => return acc + cbuffer;
      when key_minus => return acc - cbuffer;
      when key_times => return acc * cbuffer;
      when key_divide =>
      if cbuffer = zero then return zero; else return acc / cbuffer; end if;
      when others =>
      assert false
      report "Error in behavioral description."
      severity failure;
      return zero; -- Pacify compiler.
      end case;
      end function;

      procedure fatal (constant message:in string) is
      begin
      report "Error in behavioral description: " & message;
      assert false
      report "Execution stopping."
      severity failure;
      end procedure;

      -- Set a std_logic_vector signal to zero.
      procedure clr (signal a :inout std_logic_vector) is
      begin for i in a'range loop a(i) <= '0'; end loop; end;

      -- Set a std_logic_vector signal to an integer.
      procedure set(signal a: inout std_logic_vector; constant i: in integer) is
      begin a <= to_stdlogicvector(i,a'length); end;

      begin

      display_val <= cbuffer;

      -- Turn beep on when command by other process and off when timer
      -- reaches zero.
      process
      begin
      wait until falling_edge(clk);
      if reset = '1' then
      beep_ack <= '0'; beep <= '0'; clr(beep_time);
      elsif ( beep_ack xor beep_req ) = '1' then
      beep_ack <= not beep_ack; set(beep_time,20); beep <= '1';
      else
      if beep_time /= zero
      then beep_time <= beep_time - 1;
      else beep <= '0'; end if;
      end if;
      end process;

      process
      variable nl: std_logic;
      variable key_type: key_t; -- Key category.
      -- Note: next_state a variable because signals updated at end of time step.
      variable next_state: state_t;

      procedure add_digit is
      begin
      if cbuffer < buffer_max then
      cbuffer <= cbuffer * 10
      + std_logic_vector(key_code) - std_logic_vector(key_0);
      end if;
      end procedure;

      procedure do_beep is
      begin
      beep_req <= not beep_req;
      next_state := state;
      end procedure;

      procedure do_clear is
      begin
      clr(acc); clr(cbuffer); next_state := st_0N;
      end procedure;

      begin
      wait until rising_edge(clk);
      if reset = '1' then
      beep_req <= '0';
      nl := '0';
      state <= st_0N;
      clr(cbuffer);
      clr(acc);
      pending_op <= key_never;
      elsif key_code = key_none then
      nl := '1';
      elsif nl = '1' then
      nl := '0';

      case key_code is

      when key_0 | key_1 | key_2 | key_3 | key_4
      | key_5 | key_6 | key_7 | key_8 | key_9 =>
      key_type := kty_digit;

      when key_plus | key_minus | key_times | key_divide =>
      key_type := kty_arith;

      when others =>
      key_type := key_code;

      end case ;

      case state is

      when st_0N =>
      case key_type is
      when kty_digit => add_digit; next_state := st_0P;
      when key_clear => do_clear;
      when others => do_beep;
      end case;

      when st_0P =>
      case key_type is
      when kty_digit => add_digit; next_state := state;
      when kty_arith => pending_op <= key_code;
      acc <= cbuffer;
      clr(cbuffer);
      next_state := st_1N;
      when key_clear => do_clear;
      when others => do_beep;
      end case;

      when st_0C =>
      case key_type is
      when kty_digit => clr(cbuffer);
      wait for 0 ns;
      add_digit;
      next_state := st_0P;
      when kty_arith => pending_op <= key_code;
      acc <= cbuffer;
      clr(cbuffer);
      next_state := st_1N;
      when key_clear => do_clear;
      when others => do_beep;
      end case;

      when st_1N =>
      case key_type is
      when kty_digit => add_digit; next_state := st_1P;
      when key_clear => do_clear;
      when others => do_beep;
      end case;

      when st_1P =>
      case key_type is
      when kty_digit => add_digit; next_state := state;
      when key_equal => cbuffer <= do_op; next_state := st_0C;
      when kty_arith => acc <= do_op;
      pending_op <= key_code;
      clr(cbuffer);
      next_state := st_1N;
      when key_clear => do_clear;
      when others => do_beep;
      end case;

      when others =>
      fatal("Unknown case."

      end case;

      state <= next_state;

      end if;

      end process;

      end a1;


      --- Calculator Testbench (Demo, not really a test.)

      library ieee;
      use ieee.std_logic_1164.all;
      library Std_DevelopersKit;
      use Std_DevelopersKit.Std_Regpak.all;
      use Std_DevelopersKit.Std_IOpak.all;
      use work.calc_defs.all;

      entity calctb is end;

      architecture a1 of calctb is
      constant prec : integer:= 30;
      signal display : std_logic_vector ( prec-1 downto 0 );
      signal key : key_t;
      signal clk, reset, beep : std_logic:= '0';

      begin

      c:entity work.calc(a1)
      generic map (prec)
      port map (display,beep,key,reset,clk);

      clk <= not clk after 2 ns;

      process(beep)
      begin
      if beep = '1' then
      report "Beep starting.";
      elsif beep = '0' then
      report "Beep finished.";
      end if;
      end process;

      process
      variable initialized: integer:= 0;
      type key_array_t is array ( character'low to character'high ) of key_t;
      variable to_key: key_array_t;

      procedure command (constant cmd: in string) is
      variable c: character;

      begin

      if initialized /= 1 then

      for i in to_key'range loop to_key(i) := key_never; end loop;
      for i in 0 to 9 loop
      to_key( character'val((i+character'pos('0&# 039)) ) :=
      key_t(std_logic_vector(key_0) + i);
      end loop;

      to_key('+&#039:= key_plus;
      to_key('-&#039:= key_minus;
      to_key('/&#039:= key_divide;
      to_key('*&#039:= key_times;
      to_key('=&#039:= key_equal;
      to_key('c&#039:= key_clear;
      to_key(' &#039:= key_none;
      to_key(character'val(0)):= key_none;

      initialized:= 1;

      end if;

      for i in cmd'range loop

      c:= cmd(i);

      wait until rising_edge(clk);
      wait until falling_edge(clk);

      key <= to_key( c );

      wait until rising_edge(clk);
      wait until falling_edge(clk);

      assert key /= key_never
      report "Demo error: illegal key in command: " & to_string(c) & c
      severity failure;

      assert key = key_none
      report "Key " & c & " Display " & to_string(to_integer(display))
      severity note;

      wait until rising_edge(clk);
      wait until falling_edge(clk);

      key <= key_none;

      end loop;

      end procedure;

      begin

      reset <= '0';
      for i in 0 to 1 loop wait until falling_edge(clk); end loop;
      reset <= '1';
      for i in 0 to 1 loop wait until falling_edge(clk); end loop;
      reset <= '0';
      for i in 0 to 1 loop wait until falling_edge(clk); end loop;

      command("c 5 c 12 + 34 = "

      command(" 1 + 2 + 3 ++ 4 = - 10 = "

      assert false
      report "Done with tests"
      severity failure;

      end process;

      end a1;

      دیدگاه


        #4
        پاسخ : پروژه ماشین حساب fpga

        سلام آقای کوروش. من هم یه پروژه تقریبا مشابه شما دارم. اصلا تو VHDL مشکل دارم میشه بگید برای برنامه نویسی اصلا از کجا شروع کنم. :angry: :angry: :angry:

        دیدگاه

        لطفا صبر کنید...
        X