کد:
/*****************************************************
This program was produced by the
CodeWizardAVR V2.05.0 Professional
Automatic Program Generator
© Copyright 1998-2010 Pavel Haiduc, HP InfoTech s.r.l.
http://www.hpinfotech.com
Project :
Version :
Date : 25/04/2013
Author : NeVaDa
Company :
Comments:
Chip type : ATmega8
Program type : Application
AVR Core Clock frequency: 8.000000 MHz
Memory model : Small
External RAM size : 0
Data Stack size : 256
*****************************************************/
#include <mega8.h>
#include <bcd.h>
#include <io.h>
#include <delay.h>
#define set(port,pin) port |= (1<<pin)
#define reset(port,pin) port &= ~(1<<pin)
#define n_eeprom 42
#define RF_in PIND.7
#define TST1 PIND.6
#define TST2 PIND.6
#define TST3 PIND.6
#define TST4 PIND.6
#define LRN PIND.5
#define LED PORTB.7
#define OUT1 PORTC.0
#define OUT2 PORTC.1
#define OUT3 PORTC.2
#define OUT4 PORTC.3
#define OUT5 PORTB.0
#define OUT6 PORTB.1
#define OUT7 PORTB.2
#define OUT8 PORTB.6
#define NO_KEY 0
#define ALL_ERASE 1
#define ON_ERASE 2
#define SET_REMUT 3
bit f_read,f_write,f_remut,f_ok;
unsigned char index,d_crc,KEY,d_key,remut,i;
unsigned char d_in[4],crc_in[4];
unsigned int d_clar,d_time,d_led,clar_kay;
bit f_bit,f_start;
unsigned char level0,level1,d_remut[4];
eeprom char n_remut,t_remut,d_ee[n_eeprom][3];
// Timer1 output compare A interrupt service routine
interrupt [TIM1_COMPA] void timer1_compa_isr(void)
{
d_clar++;
if(d_clar > 100)
{
remut = 0;
d_clar = 0;
d_crc = 0;
d_remut[0] = 0;
d_remut[1] = 0;
d_remut[2] = 0;
//if(KEY == SET_REMUT && n_remut == n_eeprom) KEY = NO_KEY;
if(f_write)
{
f_write = 0;
KEY = NO_KEY;
}
}
if(clar_kay > 0)
clar_kay --;
else
{
KEY = NO_KEY;
d_key = 0;
}
if(d_led > 0)
d_led--;
else
{
if(KEY == ALL_ERASE)
d_led = 50 ;
else if(KEY == ON_ERASE)
d_led = 100;
else if(KEY == SET_REMUT)
d_led = 200;
else
d_led = 1000;
}
if(d_led <= 50) LED = 1; else LED = 0;
if(d_time > 0)
d_time--;
else
{
if(TST1)OUT1 = 0;
if(TST2)OUT2 = 0;
if(TST3)OUT3 = 0;
if(TST4)OUT4 = 0;
}
}
// Timer2 output compare interrupt service routine
interrupt [TIM2_COMP] void timer2_comp_isr(void)
{
if(RF_in)
{ if(RF_in)
{
if(f_bit == 1)
{
f_bit = 0;
if(level1 >= level0)
{
if(index < 8)
set(d_in[0],7-index);
else if(index < 16)
set(d_in[1],7-(index-8));
else if(index < 20 )
set(d_in[2],7-(index-16));
else
set(d_in[3],7-(index-16));
index++;
}
else
{
index++;
}
level1 = 0;
level0 = 0;
}
level1++;
f_start = 0;
}
else
{
if(f_start == 0)
{
f_bit = 1;
level0++;
if((level0 / level1) > 5 && !f_start)
{
f_start = 1;
if(level1 > 4 && index == 23)set(d_in[3],0);
index = 0;
f_bit = 0;
if((d_in[0] > 0 ||
d_in[1] > 0 ||
d_in[2] > 0 ||
d_in[3] > 0)&&
d_remut[0] == d_in[0] &&
d_remut[1] == d_in[1] &&
d_remut[2] == d_in[2] &&
d_remut[3] == d_in[3])
{
f_read = 1;
}
d_remut[0] = d_in[0];
d_remut[1] = d_in[1];
d_remut[2] = d_in[2];
d_remut[3] = d_in[3];
d_in[0] = 0;
d_in[1] = 0;
d_in[2] = 0;
d_in[3] = 0;
}
}
}
}
}
// Declare your global variables here
void main(void)
{
// Declare your local variables here
// Input/Output Ports initialization
// Port B initialization
// Func7=In Func6=In Func5=In Func4=In Func3=Out Func2=Out Func1=Out Func0=In
// State7=T State6=T State5=T State4=T State3=0 State2=0 State1=0 State0=T
PORTB=0x00;
DDRB=0xFF;
// Port C initialization
// Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
// State6=T State5=T State4=T State3=T State2=T State1=T State0=T
PORTC=0x00;
DDRC=0xFF;
// Port D initialization
// Func7=In Func6=In Func5=In Func4=In Func3=In Func2=In Func1=In Func0=In
// State7=T State6=T State5=T State4=T State3=T State2=T State1=T State0=T
PORTD=0xFF;
DDRD=0x00;
// Timer/Counter 0 initialization
// Clock source: System Clock
// Clock value: 8000.000 kHz
TCCR0=0x01;
TCNT0=0x00;
// Timer/Counter 1 initialization
// Clock source: System Clock
// Clock value: 8000.000 kHz
// Mode: Normal top=0xFFFF
// OC1A output: Set
// OC1B output: Set
// Noise Canceler: On
// Input Capture on Falling Edge
// Timer1 Overflow Interrupt: On
// Input Capture Interrupt: On
// Compare A Match Interrupt: On
// Compare B Match Interrupt: On
TCCR1A=0x00;
TCCR1B=0x0B;
TCNT1H=0x00;
TCNT1L=0x00;
ICR1H=0x00;
ICR1L=0x00;
OCR1AH=0x00;
OCR1AL=0xFA;
OCR1BL=0x00;
// Timer/Counter 2 initialization
// Clock source: System Clock
// Clock value: 8000.000 kHz
// Mode: Normal top=0xFF
// OC2 output: Set on compare match
ASSR=0x00;
TCCR2=0x02;
TCNT2=0x00;
OCR2=0x64;
// External Interrupt(s) initialization
// INT0: Off
// INT1: Off
MCUCR=0x00;
// Timer(s)/Counter(s) Interrupt(s) initialization
TIMSK=0x90;
// USART initialization
// USART disabled
UCSRB=0x00;
// Analog Comparator initialization
// Analog Comparator: Off
// Analog Comparator Input Capture by Timer/Counter 1: Off
ACSR=0x80;
SFIOR=0x00;
// ADC initialization
// ADC disabled
ADCSRA=0x00;
// SPI initialization
// SPI disabled
SPCR=0x00;
// TWI initialization
// TWI disabled
TWCR=0x00;
// Watchdog Timer initialization
// Watchdog Timer Prescaler: OSC/2048k
#pragma optsize-
WDTCR=0x1F;
WDTCR=0x0F;
#ifdef _OPTIMIZE_SIZE_
#pragma optsize+
#endif
// Global enable interrupts
#asm("sei")
while (1)
{ if(LRN)
{
if(KEY == NO_KEY)
{
d_key = 0;
}
else if(KEY == SET_REMUT)
{
d_key = 50;
}
else if(KEY == ON_ERASE)
{
d_key = 100;
}
}
else
{
clar_kay = 5000;
if(d_key < 250)
{
d_key++;
delay_ms(50);
}
if(KEY == NO_KEY && d_key > 50)
{
KEY = SET_REMUT;
d_led = 0;
}
else if(KEY == SET_REMUT && d_key > 100)
{
KEY = ON_ERASE;
d_led = 0;
}
else if(KEY == ON_ERASE && d_key > 150)
{
KEY = ALL_ERASE;
n_remut = 0;
delay_ms(10);
for(i=0;i<n_eeprom;i++)
{
d_ee[i][0] = 0;
delay_ms(10);
d_ee[i][1] = 0;
delay_ms(10);
d_ee[i][2] = 0;
delay_ms(10);
}
d_key = 0;
KEY = NO_KEY;
clar_kay = 0;
}
}
if(f_read)
{
f_read = 0;
//if(!PIND.7)printf("%u %u %u %u\n\r",d_remut[0],d_remut[1],d_remut[2],d_remut[3]);
if(d_remut[0] == crc_in[0] && d_remut[1] == crc_in[1] && d_remut[2] == crc_in[2] && d_remut[3] == crc_in[3])
{
d_crc++;
d_clar = 0;
if(KEY != NO_KEY)clar_kay = 5000;
if(d_crc == 1 && KEY == NO_KEY && !f_write)
{
d_crc = 0;
for(i=0;i<n_remut;i++)
{
if(d_remut[0] == d_ee[i][0] && d_remut[1] == d_ee[i][1] && d_remut[2] == d_ee[i][2])
{
remut = d_remut[3];
}
}
}
else if(d_crc == 20 && (KEY == SET_REMUT || KEY == ON_ERASE) && !f_write)
{
d_crc = 0;
f_write = 1;
if(KEY == SET_REMUT)
{
KEY = NO_KEY;
for(i=0;i<n_remut;i++)
{
if(d_remut[0] == d_ee[i][0] && d_remut[1] == d_ee[i][1] && d_remut[2] == d_ee[i][2])
f_ok = 1;
}
if(!f_ok && n_remut < n_eeprom)
{
n_remut++;
delay_ms(10);
if(n_remut == 1)
{
t_remut = d_remut[3];
delay_ms(10);
}
d_ee[n_remut-1][0] = d_remut[0];
delay_ms(10);
d_ee[n_remut-1][1] = d_remut[1];
delay_ms(10);
d_ee[n_remut-1][2] = d_remut[2];
delay_ms(10);
}
f_ok = 0;
}
else if(KEY == ON_ERASE)
{
for(i = 1 ; i <= n_remut ; i++)
{
if(d_remut[0] == d_ee[i-1][0] && d_remut[1] == d_ee[i-1][1] && d_remut[2] == d_ee[i-1][2])
{
f_ok = 1;
}
if(f_ok)
{
d_ee[i-1][0] = d_ee[i][0];
delay_ms(10);
d_ee[i-1][1] = d_ee[i][1];
delay_ms(10);
d_ee[i-1][2] = d_ee[i][2];
delay_ms(10);
}
}
if(f_ok)
{
n_remut--;
delay_ms(10);
}
f_ok = 0;
KEY = NO_KEY;
}
}
}
else
{
d_crc = 0;
crc_in[0] = d_remut[0];
crc_in[1] = d_remut[1];
crc_in[2] = d_remut[2];
crc_in[3] = d_remut[3];
}
}
switch (remut)
{
case 0:
f_remut = 0;
// OUT1 = 0;
// OUT2 = 0;
// OUT3 = 0;
// OUT4 = 0;
break;
case 1:
if(!f_remut)
{
f_remut = 1;
if(TST1)
{
OUT1 = 1;
d_time = t_remut * 50;
}
else
OUT1 = !OUT1;
}
break;
case 2:
if(!f_remut)
{
f_remut = 1;
if(TST2)
{
OUT2 = 1;
d_time = t_remut * 50;
}
else
OUT2 = !OUT2;
}
break;
case 4:
if(!f_remut)
{
f_remut = 1;
if(TST3)
{
OUT3 = 1;
d_time = t_remut * 50;
}
else
OUT3 = !OUT3;
}
break;
case 8:
if(!f_remut)
{
f_remut = 1;
if(TST4)
{
OUT4 = 1;
d_time = t_remut * 50;
}
else
OUT4 = !OUT4;
}
break;
}
}
}