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#include "AT91RM9200.h" #include "lib_AT91RM9200.h" // [DOC1768.PDF 23.6.9 PMC Clock Generator PLL A Register] // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 // +----+----+----+----+----+------------------------------------------------------+ // | - | - | - | - | - | MULA | // +----+----+----+----+----+------------------------------------------------------+ // // 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 // +---------+-----------------------------+---------------------------------------+ // | OUTA | PLLACOUNT | DIVA | // +---------+-----------------------------+---------------------------------------+ // // :DIVA: Divider A // 0 = Divider output is 0 // 1 = Divider is bypassed // 2 - 255 = Divider output is the Main Clock divided by DIVA. // // :PLLACOUNT: PLL A Counter // Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR // after CKGR_PLLAR is written. // // :OUTA: PLL A Clock Frequency Range // 0 0 : 80 MHz to 160 MHz // 0 1 : Reserved // 1 0 : 150 MHz to 240 MHz // 1 1 : Reserved // // :MULA: PLL A Multiplier // 0 = The PLL A is deactivated. // 1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1. // [DOC1768.PDF 23.6.11 PMC Master Clock Register] // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 // +-------------------------------------------------------------------------------+ // | - | // +-------------------------------------------------------------------------------+ // // 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 // +-----------------------------+---------+--------------+--------------+---------+ // | - | MDIV | - | PRES | CSS | // +-----------------------------+---------+--------------+--------------+---------+ // // :CSS: Master Clock Selection // 0 0 = Slow Clock is selected // 0 1 = Main Clock is selected // 1 0 = PLL A Clock is selected // 1 1 = PLL B Clock is selected // // :PRES: Master Clock Prescaler // 0 0 0 = Selected clock // 0 0 1 = Selected clock divided by 2 // 0 1 0 = Selected clock divided by 4 // 0 1 1 = Selected clock divided by 8 // 1 0 0 = Selected clock divided by 16 // 1 0 1 = Selected clock divided by 32 // 1 1 0 = Selected clock divided by 64 // 1 1 1 = Reserved // // :MDIV: Master Clock Division (on ARM9-based systems only) // 0 = The Master Clock and the Processor Clock are the same. // 1 = The Processor Clock is twice as fast as the Master Clock. // 2 = The Processor Clock is three times faster than the Master Clock. // 3 = The Processor Clock is four times faster than the Master Clock
