سلام .
من هنگام compile کردن برنامه به چنین خطایی مواجه میشم
برنامه :
و خطای داده شده
کسی میتونه بگه چطور می تونم خطا را رفع کنم
من هنگام compile کردن برنامه به چنین خطایی مواجه میشم
برنامه :
کد:
library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; package my_package is constant p:integer:=96; constant z:integer:=96; constant max_value:integer:=127; type matrix1x8 is array (1 to 8) of integer range -127 to 127; type matrix1152x8 is array (1 to 1152) of matrix1x8; type matrix1x1152i is array (1 to 1152) of integer range -127 to 127; type matrix1x1152b8 is array( 1 to 1152) of bit_vector(1 to 8); end my_package; ----------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_arith.all; use work.my_package.all; entity first_stage is port (clk:in bit;M:in matrix1152x8; out_1:out matrix1x1152i; sign_value:out matrix1x1152b8); end ; architecture behave of first_stage is signal i:integer range -127 to 127:=1; signal M_1,M_2 :matrix1x8; signal out_01 ,out_02 : integer; signal sign_value_01,sign_value_02:bit_vector(1 to 8); begin M_1<=M(1+(i-1)*p); M_2<=M(2+(i-1)*p); out_1(01+(i-1)*p)<=out_01; out_1(02+(i-1)*p)<=out_02; sign_value(1+(i-1)*p)<=sign_value_01; sign_value(2+(i-1)*p)<=sign_value_02; -- process (clk_CNP) -- --begin --if clk_CNP'event and clk_CNP='1' then -- i<=i+1; -- end if; --end process; end;
کد:
** Error: C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(22): Nonresolved signal 'out_1' has multiple sources. Drivers: C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(36):Conditional signal assignment line__36 C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(37):Conditional signal assignment line__37 ** Error: C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(23): Nonresolved signal 'sign_value' has multiple sources. Drivers: C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(40):Conditional signal assignment line__40 C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(41):Conditional signal assignment line__41 ** Error: C:/modeltech_6.4/examples/test/cnp_first_stage.vhd(49): VHDL Compiler exiting
دیدگاه