library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std_logic_textio.ALL
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
entity fir is
Port ( Din : buffer STD_LOGIC_VECTOR (15 downto 0);
Dout : buffer STD_LOGIC_VECTOR (36 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end fir;
architecture Behavioral of fir is
variable input_value,output_value : integer;
type signed_array_type is array (natural range <>

of signed(15 downto 0);
signal delayed_input : signed_array_type(0 to 40);
constant coefs : signed_array_type(0 to 40) := (
to_signed(-32,16),to_signed(519,16),to_signed(131,16),to_sign ed(-412,16),to_signed(-330,16),to_signed(473,16),to_signed(644,16),to_sig ned(-427,16),
to_signed(-1055,16),to_signed(203,16),to_signed(1537,16),to_s igned(285,16),to_signed(-2045,16),to_signed(-1169,16),to_signed(2526,16),to_signed(2741,16),
to_signed(-2923,16),to_signed(-6035,16),to_signed(3185,16),to_signed(20544,16),to _signed(29492,16),to_signed(20544,16),to_signed(31 85,16),to_signed(-6035,16),to_signed(-2923,16),
to_signed(2741,16),to_signed(2526,16),to_signed(-1169,16),to_signed(-2045,16),to_signed(285,16),to_signed(1537,16),to_s igned(203,16),to_signed(-1055,16),
to_signed(-427,16),to_signed(644,16),to_signed(473,16),to_sig ned(-330,16),to_signed(-412,16),to_signed(131,16),to_signed(519,16),to_sig ned(-32,16));
-- FIR Filter Fixed-Point Coefficients:
-- -32,519,131,-412,-330,473,644,-427,
-- -1055,203,1537,285,-2045,-1169,2526,2741,
-- -2923,-6035,3185,20544,29492,20544,3185,-6035,-2923,
-- 2741,2526,-1169,-2045,285,1537,203,-1055,
-- -427,644,473,-330,-412,131,519,-32
begin
delay_proc: process(clk,reset)
file input_file : text is in "filter_input.txt";
variable in_line : line;
begin
--------------------------------------------------
if not endfile(input_file) then
--************************************
readline(input_file,in_line);
read(in_line,input_value);
--************************************
DIN <= std_logic_vector(to_signed(input_value,16));
-----------------------------------------------
if reset = '1' then
for i in 0 to 40 loop
delayed_input(i) <= to_signed(0,16);
end loop;
elsif clk'event and clk = '1' then
delayed_input(1 to 40) <= delayed_input(0 to 39);
delayed_input(0) <= signed(Din);
end if;
end if;
end process;
--**************************************
mul_proc: process(clk)
file output_file : text is out "filter_output.txt";
variable out_line : line;
variable tmp_mul : signed(30 downto 0);
variable result : signed(36 downto 0);
begin
if not endfile(input_file) then
result := to_signed(0,37);
if clk'event and clk = '1' then
for i in 0 to 40 loop
tmp_mul := coefs(i) * delayed_input(i);
result := result + resize(tmp_mul,37);
end loop;
Dout <= std_logic_vector(result);
output_value := to_integer(signed(Dout));
--*********************************
write(out_line,output_value);
writeline(output_file,out_line);
--************************************
end if;
end if;
end process;
end Behavioral;