سلام ..
من یه برنامه تو محیط ISE 14.3 نوشتم که 33 زیر برنامه داره اما یه مشکلی دارم اونم اینکه چند تا اخطار دارم که اجازه نمیده برنامم شبیه سازی بشه .البته این مشکلو تو برنامه های کوچکترم داشتم اما نمیتونم حلش کنم ..میتونید کمکم کنید علت و بفهمم؟
ممنونم
WARNING:Xst:37 - Detected unknown constraint/property " package_net". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <ind_butterfly<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <out_sig<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <b2/d_30> of sequential type is unconnected in block <synth_main>.
ممنونم
玛丽
من یه برنامه تو محیط ISE 14.3 نوشتم که 33 زیر برنامه داره اما یه مشکلی دارم اونم اینکه چند تا اخطار دارم که اجازه نمیده برنامم شبیه سازی بشه .البته این مشکلو تو برنامه های کوچکترم داشتم اما نمیتونم حلش کنم ..میتونید کمکم کنید علت و بفهمم؟
ممنونم
WARNING:Xst:37 - Detected unknown constraint/property " package_net". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:647 - Input <ind_butterfly<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <out_sig<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <b2/d_30> of sequential type is unconnected in block <synth_main>.
ممنونم
玛丽
دیدگاه