library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Top is
Port ( clk : in STD_LOGIC;
sData : in STD_LOGIC;
sClk : in STD_LOGIC;
Dout : out STD_LOGIC
);
end Top;
architecture Behavioral of Top is
signal start,p_start,sDout : std_logic := '0';
signal DataIn : std_logic_vector(0 to 99) := (others => '0');
begin
Receive_proc: process(sclk)
variable i : integer range 0 to 100 := 0;
begin
if rising_edge(sClk) then
DataIn(i) <= sData;
if i = 99 then
start <= '1';
i := 0;
else
start <= '0';
i := i + 1;
end if;
end if;
end process;
Send_proc: process(clk)
variable Send : std_logic := '0';
variable i : integer range 0 to 100 := 0;
begin
if rising_edge(clk) then
p_start <= start;
if p_start = '0' and start = '1' then
Send := '1';
sDout <= DataIn(i);
i := i + 1;
elsif i = 100 then
i := 0;
Send := '0';
elsif Send = '1' then
sDout <= DataIn(i);
i := i + 1;
end if;
end if;
end process;
Dout <= sDout;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Top IS
END tb_Top;
ARCHITECTURE behavior OF tb_Top IS
COMPONENT Top
PORT(
clk : IN std_logic;
sData : IN std_logic;
sClk : IN std_logic;
Dout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal sData : std_logic := '0';
signal sClk : std_logic := '0';
--Outputs
signal Dout : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant sClk_period : time := 100 ns;
signal sda : std_logic_vector(0 to 99) := X"FEDCBA9876543210FEDCBA987";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Top PORT MAP (
clk => clk,
sData => sData,
sClk => sClk,
Dout => Dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sClk_process :process
begin
sClk <= '0';
wait for sClk_period/2;
sClk <= '1';
wait for sClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
Receive_proc: process(sClk)
variable i : integer range 0 to 100 := 0;
begin
if rising_edge(sClk) then
if i = 100 then
-- i := 0;
else
sData <= sda(i);
i := i + 1;
end if;
end if;
end process;
END;
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