سلام
من ميخوام طبق مراحل زير نصب کنم...
1- ابتدا بر روي icon نصب کليک کنيد.
2-license manager رو نصب کنيد.فقط next بزنيد.!!!!! در پنجره اي که فايل ليسانس رو ميخواد cancel کنيدش.
3-در پوشه ي crack که تو dvd نرم افزار هست دوتا فايل داره.اونا رو تو جايي که license manager رو نصب کرديد کپي کنيد.( خطا داد که جاي فايل ها رو عوض مي کنيم و از اين حرف ها ، عوض کنيد.)
4-از منوي all programmes در ويندوز License Server Configuration Utility را که با license manager نصب شده انتخاب کنيد و در پنجره ي باز شده از جايي که license manager رو نصب کرديد فايل license123.lic رو باز کنيد.
5-next
6- در پنجره ي جديد به جاي host name اسم کامپيوتر خودتون رو بنويسيد. click راست روي my computer کني اسم کامپيوتر رو مي توني پيدا کني تو properties.
next -7 رو که بزني مينويسه starting... و بعدش finished رومي زني.
8- کامپيوتر رو restart کن.
9-دوباره setup رو بزن و اين دفعه orcad رو نصب کن (product installation )
next -10
11- دو تا گزينه ي all orcad 16.3 products و all spb 16.3 products رو حتما انتخاب کن.
12- صبر -------------------------------next -------------- next صبر ... - finished.
13-از پوشه ي crack سه تا فايل رو توي پوشه ي cadensce که الان نصب کردي کپي کن.(توي اين پوشه الان lisence manager و spb... ديده ميشه)
14- run me.bat يا يه همچين چيزي اسم يکي از اين فايل هاست رو اجرا کن.
15- صبر زياد.به هيچ برنامه اي هم دست نزن.
16- برنامه ي capture رو اجرا کن .تمام.
تو مرحله اول license manager اين اخطار رو ميده:

بعد که اين فايل C:\Cadence\LicenseManager\license.dat رو باز ميکنم اينو نوشته:
کد:
 1:15:34 (lmgrd) -----------------------------------------------
 1:15:34 (lmgrd)  Please Note:
 1:15:34 (lmgrd) 
 1:15:34 (lmgrd)  This log is intended for debug purposes only.
 1:15:34 (lmgrd)  In order to capture accurate license
 1:15:34 (lmgrd)  usage data into an organized repository,
 1:15:34 (lmgrd)  please enable report logging. Use Macrovision's
 1:15:34 (lmgrd)  software license administration solution,
 1:15:34 (lmgrd)  FLEXnet Manager, to readily gain visibility
 1:15:34 (lmgrd)  into license usage data and to create
 1:15:34 (lmgrd)  insightful reports on critical information like
 1:15:34 (lmgrd)  license availability and usage. FLEXnet Manager
 1:15:34 (lmgrd)  can be fully automated to run these reports on
 1:15:34 (lmgrd)  schedule and can be used to track license
 1:15:34 (lmgrd)  servers and usage across a heterogeneous
 1:15:34 (lmgrd)  network of servers including Windows NT, Linux
 1:15:34 (lmgrd)  and UNIX. Contact Macrovision at
 1:15:34 (lmgrd)  www.macrovision.com for more details on how to
 1:15:34 (lmgrd)  obtain an evaluation copy of FLEXnet Manager
 1:15:34 (lmgrd)  for your enterprise.
 1:15:34 (lmgrd) 
 1:15:34 (lmgrd) -----------------------------------------------
 1:15:34 (lmgrd) 
 1:15:34 (lmgrd) 
 1:15:34 (lmgrd) pid 184
 1:15:34 (lmgrd) Done rereading
 1:15:34 (lmgrd) FLEXnet Licensing (v10.8.6.0 build 54892 i86_n3) started on POUYA-PC (IBM PC) (11/7/2014)
 1:15:34 (lmgrd) Copyright (c) 1988-2007 Macrovision Europe Ltd. and/or Macrovision Corporation. All rights reserved.
1:15:34 (lmgrd) US Patents 5,390,297 and 5,671,412. 1:15:34 (lmgrd) World Wide Web: http://www.macrovision.com 1:15:34 (lmgrd) License file(s): C:\Cadence\LicenseManager\license.dat 1:15:34 (lmgrd) lmgrd tcp-port 5280 1:15:34 (lmgrd) Starting vendor daemons ... 1:15:34 (lmgrd) Started cdslmd (pid 1772) 1:15:34 (cdslmd) FLEXnet Licensing version v10.8.5.0 build 31891 i86_n3 1:15:34 (cdslmd) Using options file: ".exe" 1:15:34 (cdslmd) Server started on POUYA-PC for: 100 1:15:34 (cdslmd) 111 206 207 1:15:34 (cdslmd) 250 251 274 1:15:34 (cdslmd) 276 279 283 1:15:34 (cdslmd) 300 305 312 1:15:34 (cdslmd) 314 316 318 1:15:34 (cdslmd) 322 336 365 1:15:34 (cdslmd) 370 371 373 1:15:34 (cdslmd) 501 550 570 1:15:34 (cdslmd) 920 940 945 1:15:34 (cdslmd) 950 963 964 1:15:34 (cdslmd) 965 966 972 1:15:34 (cdslmd) 974 991 994 1:15:34 (cdslmd) 995 11400 12141 1:15:34 (cdslmd) 12500 14000 14010 1:15:34 (cdslmd) 14020 14040 14101 1:15:34 (cdslmd) 14111 14120 14130 1:15:34 (cdslmd) 14140 20120 20121 1:15:34 (cdslmd) 20122 20123 20124 1:15:34 (cdslmd) 20127 20128 20220 1:15:34 (cdslmd) 20221 20222 20227 1:15:34 (cdslmd) 21060 21200 21400 1:15:34 (cdslmd) 21900 21920 22650 1:15:34 (cdslmd) 22800 22810 24015 1:15:34 (cdslmd) 24025 24100 24205 1:15:34 (cdslmd) 26000 32140 32150 1:15:34 (cdslmd) 32190 32500 32501 1:15:34 (cdslmd) 32502 32510 32550 1:15:34 (cdslmd) 32600 32610 32620 1:15:34 (cdslmd) 32630 32640 32760 1:15:34 (cdslmd) 33010 33301 34500 1:15:34 (cdslmd) 34510 37100 40020 1:15:34 (cdslmd) 40030 40040 40500 1:15:34 (cdslmd) 41000 50000 50010 1:15:34 (cdslmd) 50110 50200 51022 1:15:34 (cdslmd) 51023 51060 51070 1:15:34 (cdslmd) 51170 61300 61400 1:15:34 (cdslmd) a2dxf ABIT actomd 1:15:34 (cdslmd) adv_package_designer adv_package_designer_expert adv_package_engineer_expert 1:15:34 (cdslmd) advanced_package_designer Advanced_Pkg_Engineer_3D ALL_EBD 1:15:34 (cdslmd) Allego_design_expert Allegro_Design_Editor_620 Allegro_design_expert 1:15:34 (cdslmd) Allegro_Designer Allegro_Designer_Package_620 Allegro_designer_suite 1:15:34 (cdslmd) allegro_dfa allegro_dfa_att Allegro_Expert 1:15:34 (cdslmd) allegro_non_partner Allegro_Package_620 Allegro_Package_Designer_620 1:15:34 (cdslmd) Allegro_Package_Designer_XL_II Allegro_Package_SI_620 Allegro_Package_SI_620_Suite 1:15:34 (cdslmd) Allegro_Package_SI_L_II Allegro_Packager_Designer_620 Allegro_PCB 1:15:34 (cdslmd) Allegro_PCB_Design_230 Allegro_PCB_Design_620 Allegro_PCB_Design_GXL 1:15:34 (cdslmd) Allegro_PCB_Design_Planner Allegro_PCB_Editor_GXL Allegro_PCB_Global_Route_Env 1:15:34 (cdslmd) Allegro_PCB_Intercon_Feas Allegro_PCB_Intercon_Flow_Desn Allegro_PCB_Partitioning 1:15:34 (cdslmd) Allegro_PCB_RF Allegro_PCB_Router_210 Allegro_PCB_Router_230 1:15:34 (cdslmd) Allegro_PCB_Router_610 Allegro_PCB_SI_230 Allegro_PCB_SI_620 1:15:34 (cdslmd) Allegro_PCB_SI_630 Allegro_PCB_SI_630_Suite Allegro_PCBSI_Backplane 1:15:34 (cdslmd) Allegro_PCBSI_Performance Allegro_PCBSI_SerialLink Allegro_PCBSI_SParams 1:15:34 (cdslmd) Allegro_performance Allegro_Pkg_Designer_620 Allegro_Pkg_Designer_620_Suite 1:15:34 (cdslmd) Allegro_RF_Modules_option_630 Allegro_SIP_Designer_630 Allegro_SLPS 1:15:34 (cdslmd) Allegro_studio allegro_symbol Allegro_Viewer_Plus 1:15:34 (cdslmd) allegroprance AllegroSLPS AMD_MACH 1:15:34 (cdslmd) ANALOG_WORKBENCH APD apd1 1:15:34 (cdslmd) APR-HPPA archiver arouter 1:15:34 (cdslmd) Artist_Optimizer Artist_Statistics Atmel_ATV 1:15:34 (cdslmd) AWB_BEHAVIOR AWB_DIST_SIM AWB_MAGAZINE 1:15:34 (cdslmd) AWB_MAGNETICS AWB_MIX AWB_PPLOT 1:15:34 (cdslmd) AWB_RESOLVE_OPT AWB_SIMULATOR AWB_SMOKE 1:15:34 (cdslmd) AWB_SPICEPLUS AWB_STATS AWBAA 1:15:34 (cdslmd) AWBAdvancedAnalysis AWBSimulator Base_Digital_Body_Lib 1:15:34 (cdslmd) Base_Verilog_Lib BoardQuest_Team Cadence_3D_Design_Viewer 1:15:34 (cdslmd) Cadence_Chip_IO_Planner caeviews cals_out 1:15:34 (cdslmd) Capture Capture_CIS_Studio CaptureCIS 1:15:34 (cdslmd) cbds_in cdxe_in CELL3 1:15:34 (cdslmd) CELL3_ARO CELL3_CROSSTALK CELL3_CTS 1:15:34 (cdslmd) CELL3_ECL CELL3_OPENDEV CELL3_OPENEXE 1:15:34 (cdslmd) CELL3_PA CELL3_PR CELL3_QPLACE_TIMING 1:15:34 (cdslmd) CELL3_SCAN CELL3_TIMING CELL3_WIDEWIRE 1:15:34 (cdslmd) CHDL_DesignAccess Checkplus Checkplus_Expert 1:15:34 (cdslmd) CISOption Clock_Tree_Generation comp 1:15:34 (cdslmd) Composer_EDIF300_Connectivity Composer_EDIF300_Schematic ComposerCheckPlus_AdvRules 1:15:34 (cdslmd) ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev concept 1:15:34 (cdslmd) Concept_HDL_expert Concept_HDL_rules_checker Concept_HDL_studio 1:15:34 (cdslmd) ConceptHDL Concept-HDL conceptXPC 1:15:34 (cdslmd) CP_Ele_Checks cpe cpte 1:15:34 (cdslmd) CPtoolkit crefer cvtomd 1:15:34 (cdslmd) CWAVES Datapath_Preview_Option Datapath_Verilog 1:15:34 (cdslmd) Datapath_VHDL debug Device_Level_Router 1:15:34 (cdslmd) dfsverifault DICRETE_LIB DISCRETE_LIB 1:15:34 (cdslmd) DRAC2CORE DRAC2DRC DRAC2LVS 1:15:34 (cdslmd) DRAC3CORE DRAC3DRC DRAC3LVS 1:15:34 (cdslmd) DRACACCESS DRACDIST DRACERC 1:15:34 (cdslmd) DRACLPE DRACLVS DRACPG_E 1:15:34 (cdslmd) DRACPLOT DRACPRE DRACSLAVE 1:15:34 (cdslmd) dxf2a e2v EBD_edit 1:15:34 (cdslmd) EBD_floorplan EBD_power eCapture 1:15:34 (cdslmd) EDIF_Netlist_Interface EDIF_Schematic_Interface edif2ged 1:15:34 (cdslmd) edif-HPPA EMCdisplay EMControl 1:15:34 (cdslmd) expgen Extended_Digital_Body_Lib Extended_Digital_Lib 1:15:34 (cdslmd) Extended_Verilog_Lib fethman fetsetup 1:15:34 (cdslmd) FPGA_Flows FPGA_Tools Framework 1:15:34 (cdslmd) FUNCTION_LIB GATEENSEMBLE GATEENSEMBLE_ARO 1:15:34 (cdslmd) GATEENSEMBLE_CROSSTALK GATEENSEMBLE_CTS GATEENSEMBLE_CTS_LE 1:15:34 (cdslmd) GATEENSEMBLE_CTS_UL GATEENSEMBLE_ECL GATEENSEMBLE_LOWEND 1:15:34 (cdslmd) GATEENSEMBLE_OPENDEV GATEENSEMBLE_OPENEXE GATEENSEMBLE_PA 1:15:34 (cdslmd) GATEENSEMBLE_PR_LE GATEENSEMBLE_PR_UL GATEENSEMBLE_QPLACE_TIMING 1:15:34 (cdslmd) GATEENSEMBLE_SCAN GATEENSEMBLE_TIMING GATEENSEMBLE_TIMING_LE 1:15:34 (cdslmd) GATEENSEMBLE_TIMING_UL GATEENSEMBLE_UNLIMITED GATEENSEMBLE_WIDEWIRE 1:15:34 (cdslmd) gbom ged2edif glib 1:15:34 (cdslmd) gloss gphysdly gscald 1:15:34 (cdslmd) gspares HDL-DESKTOP hp3070 1:15:34 (cdslmd) IDF_Bi_Directional_Interface iges_electrical intrgloss 1:15:34 (cdslmd) intrroute intrsignoise ipc_in 1:15:34 (cdslmd) ipc_out Layout LayoutEE 1:15:34 (cdslmd) LayoutEngEd LayoutPlus LEAFPROG-SYS 1:15:34 (cdslmd) LEAPFROG-BV LEAPFROG-C LEAPFROG-CV 1:15:34 (cdslmd) LEAPFROG-SLAVE LEAPFROG-SV LEAPFROG-SYS 1:15:34 (cdslmd) LEAPFROG-VC LID10 LID11 1:15:34 (cdslmd) LINAR_LIB LINEAR-LIB LSE 1:15:34 (cdslmd) lwb MAG_LIB mdin 1:15:34 (cdslmd) mdout mdtoac mdtocv 1:15:34 (cdslmd) MIXAD_LIB multiwire Nihongoconcept 1:15:34 (cdslmd) OASIS_Simulation_Interface OpenModeler OpenModeler_SFI 1:15:34 (cdslmd) OpenModeler_SWIFT OpenSim OpenWaves 1:15:34 (cdslmd) Optimizer OrCAD_Capture_CIS_option OrCAD_EE_Designer_Plus 1:15:34 (cdslmd) OrCAD_PCB_Designer OrCAD_PCB_Designer_Basics OrCAD_PCB_Designer_PSpice 1:15:34 (cdslmd) OrCAD_PCB_Editor OrCAD_PCB_Editor_Basics OrCAD_PCB_Router 1:15:34 (cdslmd) OrCAD_Signal_Explorer OrCAD_Unison_EE OrCAD_Unison_PCB 1:15:34 (cdslmd) OrCAD_Unison_Ultra packager pcb_cursor 1:15:34 (cdslmd) PCB_design_expert PCB_design_studio PCB_designer 1:15:34 (cdslmd) pcb_editor pcb_engineer pcb_interactive 1:15:34 (cdslmd) PCB_librarian_expert pcb_prep pcb_review 1:15:34 (cdslmd) PCB_studio_variants pcomp PE_Librarian 1:15:34 (cdslmd) Pearl PIC_Utilities PICDesigner 1:15:34 (cdslmd) placement Placement_Based_Synthesis PLD 1:15:34 (cdslmd) plotVersa PowerIntegrity PPR-HPPA 1:15:34 (cdslmd) Prevail_Board_Designer Prevail_Correct_By_Design PSpice_SLPS 1:15:34 (cdslmd) PSpiceAA PSpiceAAOptimizer PSpiceAAStudio 1:15:34 (cdslmd) PSpiceAD PSpiceOptimizer PSpiceOPTIOpt 1:15:34 (cdslmd) PSpicePerfOpt PSpiceSLPSOpt PSpiceSmokeOpt 1:15:34 (cdslmd) PSpiceStudio ptc_in ptc_out 1:15:34 (cdslmd) PWM_LIB QPlace quanticout 1:15:34 (cdslmd) RapidPART rapidsim realchiplm 1:15:34 (cdslmd) redifnet rt Schematic_Generator 1:15:34 (cdslmd) sdrc_in sdrc_out shapefill 1:15:34 (cdslmd) signoise SigNoiseCS SigNoiseEngineer 1:15:34 (cdslmd) SigNoiseExpert SigNoiseStdDigLib sigxp 1:15:34 (cdslmd) Silicon_Ensemble Silicon_Ensemble_CTS Silicon_Ensemble_DSM 1:15:34 (cdslmd) Silicon_Ensemble_DSM_Crosstalk Silicon_Ensemble_OpenDev Silicon_Ensemble_OpenExe 1:15:34 (cdslmd) Silicon_Synthesis_QPBS SiliconQuest SimVision 1:15:34 (cdslmd) SiP_Digital_Architect_XL SiP_Digital_Architect_GXL SiP_Digital_Architect_GXL_II 1:15:34 (cdslmd) SiP_Digital_Layout_GXL SiP_Digital_SI_XL SiP_Digital_SI_XL_II 1:15:34 (cdslmd) SiP_RF_Architect SiP_RF_Architect_XL SiP_RF_Layout_GXL 1:15:34 (cdslmd) SiP_RF_Layout_GXL_II skillDev SPECCTRA_256U 1:15:34 (cdslmd) SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD 1:15:34 (cdslmd) SPECCTRA_autoroute SPECCTRA_DFM SPECCTRA_expert 1:15:34 (cdslmd) SPECCTRA_expert_system SPECCTRA_HP SPECCTRA_PCB 1:15:34 (cdslmd) SPECCTRA_performance SPECCTRA_QE SPECCTRA_Unison_PCB 1:15:34 (cdslmd) SPECCTRA_Unison_Ultra SPECCTRA_VT SPECCTRAQuest 1:15:34 (cdslmd) SPECCTRAQuest_EE SPECCTRAQuest_EE_SI SPECCTRAQuest_SI_expert 1:15:34 (cdslmd) SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer Spectre_ST_Models 1:15:34 (cdslmd) SpectreRF SQ_ModelIntegrity sqpkg 1:15:34 (cdslmd) swap SWIFT sx 1:15:34 (cdslmd) Synlink_Interface synSmartIF synSmartLib 1:15:34 (cdslmd) synTiOpt TOPOLOGY_EDITOR tscr.ex 1:15:34 (cdslmd) tsTestGen tsTestIntf tsTSynVHDL 1:15:34 (cdslmd) tsTSynVLOG tune tw01 1:15:34 (cdslmd) tw02 UET Unison_SPECCTRA_4U 1:15:34 (cdslmd) UNISON_SPECCTRA_6U v2e Vampire_HDRC 1:15:34 (cdslmd) Vampire_HLVS Vampire_UI verfault 1:15:34 (cdslmd) VERILOG-SLAVE VERILOG-XL VERITIME 1:15:34 (cdslmd) VERLOG-SLAVE vgen VHDLLink 1:15:34 (cdslmd) viable Virtuoso_Schem_Option visula_in 1:15:34 (cdslmd) VITAL-XL vloglink VXL-ALPHA 1:15:34 (cdslmd) VXL-LMC-HW-IF VXL-SWITCH-RC VXL-TURBO 1:15:34 (cdslmd) VXL-VCW VXL-VET VXL-VLS 1:15:34 (cdslmd) VXL-VRA wedifsch XBLOX-HPPA 1:15:34 (cdslmd) XDE-HPPA xilCds xilComposerFE 1:15:34 (cdslmd) xilConceptFE xilEdif 1:15:34 (cdslmd) 1:15:34 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines 1:15:34 (cdslmd) 1:15:34 (cdslmd) EXTERNAL FILTERS are OFF 1:15:34 (cdslmd) CANNOT OPEN options file ".exe" 1:15:34 (lmgrd) cdslmd using TCP-port 49412 1:15:34 (cdslmd) TCP_NODELAY NOT enabled 1:15:34 (cdslmd) OUT: "100" POUYA@POUYA-PC 1:15:34 (cdslmd) IN: "100" POUYA@POUYA-PC 1:15:39 (cdslmd) OUT: "100" POUYA@POUYA-PC 1:15:39 (cdslmd) IN: "100" POUYA@POUYA-PC 1:15:44 (cdslmd) OUT: "100" POUYA@POUYA-PC 1:15:44 (cdslmd) IN: "100" POUYA@POUYA-PC
خيلي گيج شدم oo: چرا همچين اخطاري ميده؟ :cry2: