library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity t3 is
Port ( clk : in STD_LOGIC;
go : in STD_LOGIC;
clr : in STD_LOGIC;
a : out STD_LOGIC);
end t3;
architecture Behavioral of t3 is
signal cunter,k : std_logic_vector(7 downto 0);
signal secend : std_logic;
signal cte : integer:=50; --for frequense 50hz
begin
process(clk)
begin
if(clk'event and clk='1')then
cunter <= k;
end if;
end process;
k <= ( others => '0' ) when clr='1' or (go='1' and cunter=cte)else
cunter+1 when go='1' else
cunter;
secend <= '1' when k=cte else
'0';
a <= secend;
end Behavioral;
Line 28: Multiple declarations of "=" included via multiple use clauses; none are made directly visibleDetermining compilation order of HDL files Line 25: Multiple declarations of "=" included via multiple use clauses; none are made directly visible Line 12: Unit <behavioral> ignored due to previous errors.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
ieee-std-1076-2000
entity ykhvm is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
go : in STD_LOGIC;
a : out STD_LOGIC);
end ykhvm;
architecture Behavioral of ykhvm is
signal cunter,k : std_logic_vector(7 downto 0);
signal secend : std_logic;
signal cte : integer:=50 ;
begin
process(clk)
begin
if(clk'event and clk='1')then
cunter <= k;
end if;
end process;
k<=(others => '0')when clr='1' or (go='1' and k=cte)else
cunter+1 when go='1' else
cunter;
secend <= '1' when k=cte else
'0';
a <= secend;
end Behavioral;
The Top module has not been specified. This can happen if no sources have been added to the project,
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