library ieee; use ieee.std_logic_1164.all; entity comparator2 is generic(n:natural:=2); port( x, y : in std_logic_vector(n - 1 downto 0); -- X is bigger, Equal, X is less respectively xb, e, xl : out std_logic ); end comparator2; library ieee; use ieee.std_logic_1164.all; entity comparator4 is generic(n:natural:=4); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end comparator4; library ieee; use ieee.std_logic_1164.all; entity comparator8 is generic(n:natural:=8); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end comparator8; library ieee; use ieee.std_logic_1164.all; entity comparator16 is generic(n:natural:=16); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end comparator16; library ieee; use ieee.std_logic_1164.all; entity comparator32 is generic(n:natural:=32); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end comparator32; architecture simple of comparator2 is signal xn, yn : std_logic_vector(n - 1 downto 0); signal xbs, es : std_logic; begin xn(1) <= not x(1); xn(0) <= not x(0); yn(1) <= not y(1); yn(0) <= not y(0); xbs <= (x(1) and yn(1)) or (x(0) and yn(1) and yn(0)) or (x(1) and x(0) and yn(0)); es <= (x(1) xnor y(1)) and (x(0) xnor y(0)); xl <= (not xbs) and (not es); xb <= xbs; e <= es; end simple; architecture simple of comparator4 is component comparator2 is generic(n:natural:=2); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end component; for all : comparator2 use entity work.comparator2(simple); signal xb1, xb0, e1, e0 : std_logic; signal xbs, es : std_logic; begin comp00 : comparator2 port map(x(n / 2 - 1 downto 0), y(n / 2 - 1 downto 0), xb0, e0, open); comp01 : comparator2 port map(x(n - 1 downto n / 2), y(n - 1 downto n / 2), xb1, e1, open); xbs <= xb1 or (e1 and xb0); es <= e1 and e0; xl <= (not xbs) and (not es); xb <= xbs; e <= es; end simple; architecture simple of comparator8 is component comparator4 is generic(n:natural:=4); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end component; for all : comparator4 use entity work.comparator4(simple); signal xb1, xb0, e1, e0 : std_logic; signal xbs, es : std_logic; begin comp00 : comparator4 port map(x(n / 2 - 1 downto 0), y(n / 2 - 1 downto 0), xb0, e0, open); comp01 : comparator4 port map(x(n - 1 downto n / 2), y(n - 1 downto n / 2), xb1, e1, open); xbs <= xb1 or (e1 and xb0); es <= e1 and e0; xl <= (not xbs) and (not es); xb <= xbs; e <= es; end simple; architecture simple of comparator16 is component comparator8 is generic(n:natural:=8); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end component; for all : comparator8 use entity work.comparator8(simple); signal xb1, xb0, e1, e0 : std_logic; signal xbs, es : std_logic; begin comp00 : comparator8 port map(x(n / 2 - 1 downto 0), y(n / 2 - 1 downto 0), xb0, e0, open); comp01 : comparator8 port map(x(n - 1 downto n / 2), y(n - 1 downto n / 2), xb1, e1, open); xbs <= xb1 or (e1 and xb0); es <= e1 and e0; xl <= (not xbs) and (not es); xb <= xbs; e <= es; end simple; architecture simple of comparator32 is component comparator16 is generic(n:natural:=16); port( x, y : in std_logic_vector(n - 1 downto 0); xb, e, xl : out std_logic ); end component; for all : comparator16 use entity work.comparator16(simple); signal xb1, xb0, e1, e0 : std_logic; signal xbs, es : std_logic; begin comp00 : comparator16 port map(x(n / 2 - 1 downto 0), y(n / 2 - 1 downto 0), xb0, e0, open); comp01 : comparator16 port map(x(n - 1 downto n / 2), y(n - 1 downto n / 2), xb1, e1, open); xbs <= xb1 or (e1 and xb0); es <= e1 and e0; xl <= (not xbs) and (not es); xb <= xbs; e <= es; end simple;
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