سلام
برنامه زیر برنامه من هست
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity v is
port (clk : in std_logic ;
o : out integer range 0 to 9);
end v;
architecture Behavioral of v is
begin
process (clk)
variable cou: integer range 0 to 9 ;
begin
if (clk'event and clk='1') then
cou :=cou + 1;
end if;
o<=cou;
end process;
end Behavioral;
این فایل ucf هست :
و error که در map میده ؟
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <clk> is placed at site <C3>. The corresponding BUFG component
<clk_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
of IOBs that can use the fast path to the Clocker buffer, and they are not
being used. You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
برنامه زیر برنامه من هست
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity v is
port (clk : in std_logic ;
o : out integer range 0 to 9);
end v;
architecture Behavioral of v is
begin
process (clk)
variable cou: integer range 0 to 9 ;
begin
if (clk'event and clk='1') then
cou :=cou + 1;
end if;
o<=cou;
end process;
end Behavioral;
NET "o[3]" LOC = P4;
NET "o[2]" LOC = N5;
NET "o[1]" LOC = P5;
NET "o[0]" LOC = M6;
NET "clk" LOC = C3;
NET "o[2]" LOC = N5;
NET "o[1]" LOC = P5;
NET "o[0]" LOC = M6;
NET "clk" LOC = C3;
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <clk> is placed at site <C3>. The corresponding BUFG component
<clk_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set
of IOBs that can use the fast path to the Clocker buffer, and they are not
being used. You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
دیدگاه