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Front Side Bus (FSB) is the bus that carries data between the CPU and the northbridge.
Depending on the processor used, some computers may also have a back side bus that connects the CPU to the cache. This bus and the cache connected to it is faster than accessing the system memory via the front side bus.
The bandwidth or maximum theoretical throughput of the front side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 32-bit (4-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 1600 megabytes per second (MB/s).
The number of transfers per clock cycle is dependent on the technology used. For example, GTL+ performs 1 transfer/cycle, EV6 2 transfers/cycle, and AGTL+ 4 transfers/cycle. Intel calls the technique of four transfers per cycle Quad Pumping.
Many manufacturers today publish the speed of the FSB in megatransfers per second (MT/s), not the FSB clock frequency in megahertz (MHz). This is because the actual speed is determined by how many transfers can be performed each clock cycle as well as by the clock frequency. For example, if a motherboard (or processor) has a FSB clocked at 200 MHz and performs 4 transfers per clock cycle, the FSB is rated at 800 MT/s.
اگه دوستان به جز این مطلب دارن ممنون میشم اینجا قرار بدن
Front Side Bus (FSB) is the bus that carries data between the CPU and the northbridge.
Depending on the processor used, some computers may also have a back side bus that connects the CPU to the cache. This bus and the cache connected to it is faster than accessing the system memory via the front side bus.
The bandwidth or maximum theoretical throughput of the front side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 32-bit (4-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 1600 megabytes per second (MB/s).
The number of transfers per clock cycle is dependent on the technology used. For example, GTL+ performs 1 transfer/cycle, EV6 2 transfers/cycle, and AGTL+ 4 transfers/cycle. Intel calls the technique of four transfers per cycle Quad Pumping.
Many manufacturers today publish the speed of the FSB in megatransfers per second (MT/s), not the FSB clock frequency in megahertz (MHz). This is because the actual speed is determined by how many transfers can be performed each clock cycle as well as by the clock frequency. For example, if a motherboard (or processor) has a FSB clocked at 200 MHz and performs 4 transfers per clock cycle, the FSB is rated at 800 MT/s.
